www.fairchildsemi.com
FAN2518, FAN2519
50 mA CMOS LDO Regulators with Fast Start Enable
Features
•
•
•
•
•
•
•
•
Ultra Low Power Consumption
Enable optimized for CDMA time phases
50 mV dropout voltage at 50 mA
25 µA ground current at 50 mA
Enable/Shutdown Control
SOT23-5 package
Thermal limiting
300 mA peak current
wide variety of external capacitors, and the compact SOT23-5
surface-mount package. In addition, the FAN2518/19 family
offer the fast power-cycle time required in CDMA handset
applications. These products offer significant improvements
over older BiCMOS designs and are pin-compatible with
many popular devices. The output is thermally protected
against overload.
The FAN2518 and FAN2519 devices are distinguished by
the assignment of pin 4:
FAN2518:
pin 4 – ADJ, allowing the user to adjust the
output voltage over a wide range using an external voltage
divider.
FAN2518-XX:
pin 4 – BYP, to which a bypass capacitor
may be connected for optimal noise performance. Output
voltage is fixed, indicated by the suffix XX.
FAN2519-XX:
pin 4 – ERR, a flag which indicates that the
output voltage has dropped below the specified minimum
due to a fault condition.
The standard fixed output voltages available are 2.5V, 2.6V,
2.7V, 2.8V, 2.85V, 3.0V, and 3.3V. Custom output voltage are
also available: please contact your local Fairchild Sales
Office for information.
Applications
•
•
•
•
Cellular Phones and accessories
PDAs
Portable cameras and video recorders
Laptop, notebook and palmtop computers
Description
The FAN2518/19 family of micropower low-dropout voltage
regulators utilize CMOS technology to offer a new level of
cost-effective performance in GSM, TDMA, and CDMA
cellular handsets, Laptop and Notebook portable computers,
and other portable devices. Features include extremely low
power consumption and low shutdown current, low dropout
voltage, exceptional loop stability able to accommodate a
Block Diagrams
EN
VIN
Bandgap
Error
Amplifier
p
VOUT
ADJ
Thermal
Sense
FAN2518
GND
FAN2518-XX
EN
VIN
Bandgap
p
VOUT
ERR
Error
Amplifier
Thermal
Sense
VIN
Bandgap
p
VOUT
EN
BYP
Error
Amplifier
GND
Thermal
Sense
FAN2519-XX
GND
REV. 1.0.6 2/14/03
PRODUCT SPECIFICATION
FAN2518/FAN2519
Pin Assignments
V
IN
GND
EN
1
5
V
OUT
2
3
4
ADJ/BYP/ERR
Pin No.
1.
2.
3.
4.
5.
FAN2518
V
IN
GND
EN
ADJ
V
OUT
FAN2518-XX
V
IN
GND
EN
BYP
V
OUT
FAN2519-XX
V
IN
GND
EN
ERR
V
OUT
Pin Descriptions
Pin Name
ADJ
BYP
ERR
Pin No.
4
4
4
Type
Input
Passive
Open drain
Pin Function Description
FAN2518 Adjust.
Ratio of potential divider from VOUT to ADJ
determines output voltage.
FAN2518-XX Bypass.
Connect 470 pF capacitor for noise reduction.
FAN2519-XX Error.
Error flag output.
0:
Output voltage < 95% of nominal.
1:
Output voltage > 95% of nominal.
Enable.
0:
Shutdown V
OUT
.
1:
Enable V
OUT
.
Voltage Input.
Supply voltage input.
Voltage Output.
Regulated output voltage.
Ground.
EN
3
Digital Input
V
IN
V
OUT
GND
1
5
2
Power in
Power out
Power
Functional Description
Designed utilizing CMOS process technology, the
FAN2518/19 family of products are carefully optimized for
use in compact battery-powered devices, offering a unique
combination of low power consumption, extremely low
dropout voltages, high tolerance for a variety of output
capacitors, and the ability to disable the output to less than
1µA under user control. In the circuit, a difference amplifier
controls the current through a series-pass P-Channel
MOSFET, comparing the load voltage at the output with an
onboard low-drift bandgap reference. The series resistance
of the pass P-Channel MOSFET is approximately 1
Ω
, result-
ing in an unusually low dropout voltage under load when
compared to older bipolar pass-transistor designs.
Protection circuitry is provided onboard for overload condi-
tions. In conditions where the device reaches temperatures
exceeding the specified maximums, an onboard circuit shuts
down the output, where it remains suspended until it has
cooled before re-enabling. The user is also free to shut down
the device using the Enable control pin at any time.
Careful design of the output regulator amplifier assures loop
stability over a wide range of ESR values in the external
output capacitor. A wide range of values and types can be
accommodated, allowing the user to select a capacitor
meeting his space, cost, and performance requirements,
and enjoy reliable operation over temperature, load, and
tolerance variations.
2
REV. 1.0.6 2/14/03
FAN2518/FAN2519
PRODUCT SPECIFICATION
An Enable pin, available on all devices, allows the user to
shut down the regulator output to conserve power, reducing
supply current to less than 1µA. The output can then be
re-Enabled within 500µSec, fulfilling the fast power-cycling
needs of CDMA applications. Depending on the model
selected, other control and status functions are available at
pin 4 to enhance the operation of the device. The adjustable-
voltage versions utilize pin 4 to connect to an external
voltage divider which feeds back to the regulator error
amplifier, thereby setting the voltage as desired. Two other
functions are available in the fixed-voltage versions: in
noise-sensitive applications, an external Bypass capacitor
connection is provided that allows the user to achieve opti-
mal noise performance at the output, while the Error output
functions as a diagnostic flag to indicate that the output
voltage has dropped more than 5% below the nominal fixed
voltage.
more. Tantalum or aluminum electrolytic, or multilayer
ceramic types can all be used. A nominal value of at least
1µF is recommended.
Bypass Capacitor (FAN2518 Only)
In the fixed-voltage configuration, connecting a capacitor
between the bypass pin and ground can significantly reduce
noise on the output. Values ranging from 470pF to 10nF can
be used, depending on the sensitivity to output noise in the
application.
At the high-impedance Bypass pin, care must be taken in the
circuit layout to minimize noise pickup, and capacitors must
be selected to minimize current loading (leakage). Noise
pickup from external sources can be considerable. Leakage
currents into the Bypass pin will directly affect regulator
accuracy and should be kept as low as possible; thus, high-
quality ceramic and film types are recommended for their
low leakage characteristics. Cost-sensitive applications not
concerned with noise can omit this capacitor.
Applications Information
External Capacitors – Selection
The FAN2518/19 allows the user to utilize a wide variety of
capacitors compared to other LDO products. An innovative
design approach offers significantly reduced sensitivity to
ESR (Effective Series Resistance), which degrades regulator
loop stability in older designs. While the improvements fea-
tured in the FAN2518/19 family greatly simplify the design
task, capacitor quality still must be considered if the designer
is to achieve optimal circuit performance. In general,
ceramic capacitors offer superior ESR performance, at a
lower cost and a smaller case size than tantalums. Those with
X7R or Y5Vdielectric offer the best temperature coefficient
characteristics. The combination of tolerance and variation
over temperature in some capacitor types can result in signif-
icant variations, resulting in unstable performance over rated
conditions.
Control Functions
Enable Pin
Applying a voltage of 0.4V or less at the Enable pin will dis-
able the output, reducing the quiescent output current to less
than 1µA, while a voltage of 2.0V or greater will enable the
device. If this shutdown function is not needed, the pin can
simply be connected to the V
IN
pin. Allowing this pin to float
will cause erratic operation.
Error Flag (FAN2519 Only)
To indicate conditions such as input voltage dropout
(low V
IN
), overheating, or overloading (excessive output
current), the ERR pin indicates a fault condition. It is an
open-drain output which is HIGH when the voltage at V
OUT
is greater than 95% of the nominal rated output voltage and
LOW when V
OUT
is less than 95% or the rated output volt-
age, as specified in the error trip level characteristics.
A logic pullup resistor of 100K
Ω
is recommended at this
output. The pin can be left disconnected if unused.
Thermal Protection
The FAN2518/19 is designed to supply high peak output
currents of up to 1A for brief periods, however this output
load will cause the device temperature to increase and
exceed maximum ratings due to power dissipation. During
output overload conditions, when the die temperature
exceeds the shutdown limit temperature of 150°C, onboard
thermal protection will disable the output until the tempera-
ture drops below this limit, at which point the output is
then re-enabled. During a thermal shutdown situation the
user may assert the power-down function at the Enable
pin, reducing power consumption to the minimum level
I
GND
· V
IN
.
Input Capacitor
An input capacitor of 2.2µF (nominal value) or greater,
connected between the Input pin and Ground, located in
close proximity to the device, will improve transient
response and noise rejection. Higher values will offer supe-
rior input ripple rejection and transient response. An input
capacitor is recommended when the input source, either a
battery or a regulated AC voltage, is located far from the
device. Any good quality ceramic, tantalum, or metal film
capacitor will give acceptable performance, however tanta-
lum capacitors with a surge current rating appropriate to the
application must be selected to avoid catastrophic failure.
Output Capacitor
An output capacitor is required to maintain regulator loop
stability. Unlike many other LDO regulators, the FAN2518/19
family of products are nearly insensitive to output capacitor
ESR. Stable operation will be achieved with a wide variety
of capacitors with ESR values ranging from 10m
Ω
to 10
Ω
or
REV. 1.0.6 2/14/03
3
PRODUCT SPECIFICATION
FAN2518/FAN2519
Thermal Characteristics
The FAN2518/19 is designed to supply 50mA at the speci-
fied output voltage with an operating die (junction) tempera-
ture of up to 125°C. Once the power dissipation and thermal
resistance is known, the maximum junction temperature of
the device can be calculated. While the power dissipation is
calculated from known electrical parameters, the thermal
resistance is a result of the thermal characteristics of the
compact SOT23-5 surface-mount package and the surround-
ing PC Board copper to which it is mounted.
The power dissipation is equal to the product of the input-to-
output voltage differential and the output current plus the
ground current multiplied by the input voltage, or:
P
D
=
(
V
IN
– V
OUT
)I
OUT
+ V
IN
I
GND
device to enter a thermal cycling loop, in which the circuit
enters a shutdown condition, cools, re-enables, and then
again overheats and shuts down repeatedly due to an
unmanaged fault condition.
Operation of Adjustable Version
The adjustable version of the FAN2518/19 includes an input
pin ADJ which allows the user to select an output voltage
ranging from 1.8V to near V
IN
, using an external resistor
divider. The voltage V
ADJ
presented to the ADJ pin is fed to
the onboard error amplifier which adjusts the output voltage
until V
ADJ
is equal to the onboard bandgap reference voltage
of 1.32V(typ). The equation is:
R
upper
V
OUT
= 1.32V
×
1 + ---------------
-
R
lower
The ground pin current I
GND
can be found in the charts
provided in the Electrical Characteristics section.
The relationship describing the thermal behavior of the
package is:
T
J
(
max
)
– T
A
P
D
(
max
)
=
-------------------------------
½
θ
JA
The total value of the resistor chain should not exceed
250K
Ω
total to keep the error amplifier biased during
no-load conditions. Programming output voltages very near
V
IN
need to allow for the magnitude and variation of the
dropout voltage V
DO
over load, supply, and temperature
variations. Note that the low-leakage FET input to the
CMOS Error Amplifier induces no bias current error to the
calculation.
where T
J(max)
is the maximum allowable junction tempera-
ture of the die, which is 125°C, and T
A
is the ambient operat-
ing temperature.
θ
JA
is dependent on the surrounding PC
board layout and can be empirically obtained. While the
θ
JC
(junction-to-case) of the SOT23-5 package is specified at
130°C /W, the
θ
JA
of the minimum PWB footprint will be at
least 235°C /W. This can be improved upon by providing a
heat sink of surrounding copper ground on the PWB.
Depending on the size of the copper area, the resulting
θ
JA
can range from approximately 180°C /W for one square inch
to nearly 130°C /W for 4 square inches. The addition of
backside copper with through-holes, stiffeners, and other
enhancements can also aid in reducing this value. The heat
contributed by the dissipation of other devices located
nearby must be included in design considerations.
Once the limiting parameters in these two relationships have
been determined, the design can be modified to ensure that
the device remains within specified operating conditions. If
overload conditions are not considered, it is possible for the
General PWB Layout Considerations
To achieve the full performance of the device, careful circuit
layout and grounding technique must be observed. Establish-
ing a small local ground, to which the GND pin, the output
and bypass capacitors are connected, is recommended, while
the input capacitor should be grounded to the main ground
plane. The quiet local ground is then routed back to the main
ground plane using feedthrough vias. In general, the high-
frequency compensation components (input, bypass, and
output capacitors) should be located as close to the device as
possible. The proximity of the output capacitor is especially
important to achieve optimal noise compensation from the
onboard error amplifier, especially during high load condi-
tions. A large copper area in the local ground will provide the
heat sinking discussed above when high power dissipation
significantly increases the temperature of the device.
Component-side copper provides significantly better thermal
performance for this surface-mount device, compared to that
obtained when using only copper planes on the underside.
4
REV. 1.0.6 2/14/03
FAN2518/FAN2519
PRODUCT SPECIFICATION
Absolute Maximum Ratings
(beyond which the device may be damaged)
1
Parameter
Power Supply Voltages
V
IN
(Measured to GND)
Enable Input (EN)
Applied voltage (Measured to GND)
2
ERR Output
Applied voltage (Measured to GND)
2
Power
Dissipation
3
Temperature
Junction
Lead Soldering (5 seconds)
Storage
Electrostatic Discharge
4
-65
4
-65
150
260
150
°C
°C
°C
kV
Internally limited
0
7
V
0
7
V
0
7
V
Min
Typ
Max
Unit
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only
if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Based upon thermally limited junction temperature:
T
J
(
max
)
– T
A
P
D
= -------------------------------
Θ
JA
4. Human Body Model is 4kV minimum using Mil Std. 883E, method 3015.7. Machine Model is 400V minimum using JEDEC
method A115-A.
Recommended Operating Conditions
Parameter
V
IN
V
OUT
V
EN
V
ERR
T
J
θ
JA
θ
JC
Input Voltage Range
Output Voltage Range, Adjustable
Enable Input Voltage
ERR Flag Voltage
Junction Temperature
Thermal resistance
Thermal resistance
-40
220
130
Min
2.7
V
REF
0
Nom
Max
6.5
V
IN
-V
DO
V
IN
V
IN
+125
Units
V
V
V
V
°C
°C/W
°C/W
REV. 1.0.6 2/14/03
5
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