5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Device Configurations and Pin-outs ............................................................................................................................................. 9
Pin-out Top Views................................................................................................................................................................. 9
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 10
Frequency Stability ............................................................................................................................................................. 16
Output Frequency and Format............................................................................................................................................ 16
Output Frequency Tuning ................................................................................................................................................... 16
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 17
Control Voltage Bandwidth ................................................................................................................................................. 20
Pull Range and Average Pull Range .................................................................................................................................. 22
Output Frequency ............................................................................................................................................................... 23
2
I C Control Registers .......................................................................................................................................................... 25
Serial Interface Configuration Description .......................................................................................................................... 28
Serial Signal Format ........................................................................................................................................................... 28
Parallel Signal Format ........................................................................................................................................................ 29
Parallel Data Format ........................................................................................................................................................... 29
2
I C Timing Specification ...................................................................................................................................................... 31
2
I C Device Address Modes ................................................................................................................................................. 32
Schematic Example ............................................................................................................................................................ 33
Dimensions and Patterns ........................................................................................................................................................... 34
Additional Information ................................................................................................................................................................ 36
Revision History ......................................................................................................................................................................... 37
Rev 1.05
Page 3 of 38
www.sitime.com
SiT5156
1 MHz to 60 MHz, ±0.5 to ±2.5 ppm, Elite Platform™ Super-TCXO
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3V Vdd.
Table 1. Output Characteristics
Parameters
Nominal Output Frequency Range
Operating Temperature Range
Symbol
F_nom
T_use
Min.
1
-20
-40
-40
Frequency Stability over
Temperature
Initial Tolerance
Supply Voltage Sensitivity
F_stab
–
–
–
F_init
F_Vdd
–
–
–
–
Output Load Sensitivity
F_load
–
–
–
Frequency vs. Temperature Slope
ΔF/ΔT
–
–
–
Dynamic Frequency Change during
Temperature Ramp
One-Year Aging
20-Year Aging
F_dynamic
–
–
–
F_1y
F_20y
–
–
Typ.
–
–
–
–
–
–
–
–
±7.10
±11.83
±28.40
±0.81
±1.35
±3.24
±15
±25
±60
±0.13
±0.21
±0.50
±1
±2
Max.
60
+70
+85
+105
±0.5
±1.0
±2.5
±1
±16.25
±32.50
±65.0
±2.75
±5.50
±11.00
±25
±50
±100
±0.21
±0.42
±0.83
–
–
Unit
MHz
°C
°C
°C
ppm
ppm
ppm
ppm
ppb
ppb
ppb
ppb
ppb
ppb
ppb/°C
ppb/°C
ppb/°C
ppb/s
ppb/s
ppb/s
ppm
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
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FPGA/CPLD
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