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PIC17C42-08/JW

Description
8-BIT, OTPROM, 33 MHz, RISC MICROCONTROLLER, PQCC44
Categorysemiconductor    The embedded processor and controller   
File Size59KB,4 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

PIC17C42-08/JW Overview

8-BIT, OTPROM, 33 MHz, RISC MICROCONTROLLER, PQCC44

PIC17C42-08/JW Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals44
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage6 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
External data bus width16
Number of input and output buses33
Line speed33 MHz
Processing package descriptionPLASTIC, LCC-44
Lead-freeYes
EU RoHS regulationsYes
China RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeSQUARE
Package SizeCHIP CARRIER
surface mountYes
Terminal formJ BEND
Terminal spacing1.27 mm
terminal coatingMATTE TIN
Terminal locationQUAD
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
Address bus width16
Number of digits8
Maximum FCLK clock frequency33 MHz
Microprocessor typeRISC MICROCONTROLLER
PWM channelYes
ROM programmingOTPROM
PIC17C44
PIC17C44 Rev. A Silicon Errata Sheet
The PIC17C44 (Rev. A) parts you have received con-
form functionally to the PIC17C4X preliminary data
sheet (DS30412
C
), except for the following clarifica-
tions and corrections.
NONE
Clarifications/Corrections to the Data Sheet:
The PIC17C44 Preliminary Data Sheet (document
DS30412
C
) that you have received, requires the follow-
ing clarifications and corrections.
1.
The clearing of any interrupt enable bit(s) in the
INTSTA register should be preceded by the dis-
abling of the global interrupt control bit (setting
GLINTD). Global interrupts may then be re-
enabled. The individual interrupts may be re-
enabled without further control of the GLINTD
bit.
When global interrupts are enabled, if the interrupt
flag is being set when the corresponding enable bit
is being cleared the device will branch to the reset
vector address (0h). The interrupt flag will not be
(automatically) cleared.
2.
The
RETURN
instruction causes an update of the
PCLATH register. The PCLATH register is
loaded with the high address of the
RETURN
instruction.
The Table write to internal program memory (self
programming) can occur even when the MCLR
pin is either at the V
IH
or V
IHH
voltage level.
When the MCLR pin is at V
IH
, the table write
sequence occurs, but the programming voltage
is marginal since the MCLR pin is not at the cor-
rect level. This table write may cause the speci-
fied program memory location to be corrupted
(depending on the data in the TABLAT register).
3.
Note:
As with any windowed EPROM device, please cover the window at all times, except when erasing.
©
October, 1997 Microchip Technology Inc.
DS30412C/44/E1A2-page 1
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