ADC08D1000QML High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
May 2007
ADC08D1000QML
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter
General Description
The ADC08D1000 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.2 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc-
ing a high 7.4 Effective Number Of Bits (ENOB) with a 498
MHz input signal and a 1 GHz sample rate while providing a
10
-18
Bit Error Rate ( B.E.R.). Output formatting is offset binary
and the Low Voltage Differential Signaling (LVDS) digital out-
puts are compliant with IEEE 1596.3-1996, with the exception
of an adjustable common mode voltage between 0.8V and
1.13V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 2 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced multi-layer ceramic quad package and operates
over the Military (-55°C
≤
T
A
≤
+125°C) temperature range.
This part will work in a radiation environment, with ex-
cellent results, provided the guidelines in applications
section 2.1 are followed.
Features
■
■
■
■
■
■
■
■
■
■
Available with radiation guarantee
Internal Sample-and-Hold
Single +1.9V ±0.1V Operation
Choice of SDR or DDR output clocking
Interleave Mode for 2x Sampling Rate
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock
Key Specifications
■
Resolution
■
Max Conversion Rate
■
Bit Error Rate
■
ENOB @ 498 MHz Input
■
DNL
■
Power Consumption
— Operating
— Power Down Mode
■
Total Ionizing Dose
■
Single Event Latch Up
1.6 W (typ)
3.5 mW (typ)
300 krad(Si)
>120 MeV/mg/cm
2
8 Bits
1 GSPS (min)
10
-18
(typ)
7.4 Bits (typ)
±0.15 LSB (typ)
Applications
■
Communication Satellites/Systems
■
Direct RF Down Conversion
© 2007 National Semiconductor Corporation
201802
www.national.com
ADC08D1000QML
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie this pin
high for normal differential DCLK and data amplitude. Ground this
pin for a reduced differential output amplitude and reduced power
consumption. See Section 1.1.6. When the extended control mode
is enabled, this pin functions as the SCLK input which clocks in the
serial data.See Section 1.2 for details on the extended control
mode. See Section 1.3 for description of the serial interface.
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the output
data transitions. (See Section 1.1.5.2). When this pin is floating or
connected to 1/2 the supply voltage, DDR clocking is enabled.
When the extended control mode is enabled, this pin functions as
the SDATA input. See Section 1.2 for details on the extended
control mode. See Section 1.3 for description of the serial
interface.
DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See Section 1.5
for detailed description.
Power Down Pins. A logic high on the PD pin puts the entire device
into the Power Down Mode. A logic high on the PDQ pin puts only
the "Q" ADC into the Power Down mode.
Calibration Cycle Initiate. A minimum 640 input clock cycles logic
low followed by a minimum of 640 input clock cycles high on this
pin initiates the self calibration sequence. See Section 2.5.2 for an
overview of self-calibration and Section 2.5.2.2 for a description of
on-command calibration.
See Section 2.1 for use in Radiation
Environments.
Full Scale Range Select and Extended Control Enable. In non-
extended control mode, a logic low on this pin sets the full-scale
differential input range to 650 mV
P-P
. A logic high on this pin sets
the full-scale differential input range to 870 mV
P-P
. See Section
1.1.4. To enable the extended control mode, whereby the serial
interface and control registers are employed, allow this pin to float
or connect it to a voltage equal to V
A
/2. See Section 1.2 for
information on the extended control mode.
See Section 2.1 for
use in Radiation Environments.
Calibration Delay, Dual Edge Sampling and Serial Interface Chip
Select. With a logic high or low on pin 14, this pin functions as
Calibration Delay and sets the number of input clock cycles after
power up before calibration begins (See Section 1.1.1). With pin
14 floating, this pin acts as the enable pin for the serial interface
input and the CalDly value becomes "0" (short delay with no
provision for a long power-up calibration delay). When this pin is
floating or connected to a voltage equal to V
A
/2, DES (Dual Edge
Sampling) mode is selected where the "I" input is sampled at twice
the input clock rate and the "Q" input is ignored. See Section
1.1.5.1.
See Section 2.1 for use in Radiation Environments.
3
OutV / SCLK
4
OutEdge / DDR /
SDATA
15
DCLK_RST
26
29
PD
PDQ
30
CAL
14
FSR/ECE
127
CalDly / DES /
SCS
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