Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive edge-trigger
74LV74
FEATURES
•
Wide operating voltage: 1.0 to 5.5V
•
Optimized for Low Voltage applications: 1.0 to 3.6V
•
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
•
Typical V
OLP
(output ground bounce)
t
0.8V @ V
CC
= 3.3V,
•
Typical V
OHV
(output V
OH
undershoot)
u
2V @ V
CC
= 3.3V,
•
Output capability: standard
•
I
CC
category: flip-flops
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
=t
f
v2.5
ns
SYMBOL
PARAMETER
t
PHL
/t
PLH
Propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
Maximum clock frequency
Input capacitance
Power dissipation capacitance per flip-flop
T
amb
= 25°C
T
amb
= 25°C
DESCRIPTION
The 74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The 74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
D
) and (R
D
)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
CONDITIONS
C
L
= 15pF
V
CC
= 3.3V
C
L
= 15pF
V
CC
= 3.3V
Notes 1 and 2
TYPICAL
11
14
14
76
3.5
24
UNIT
ns
f
max
C
I
C
PD
MHz
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
V
CC2
x f
i
)S
(C
L
V
CC2
f
o
) where:
P
D
= C
PD
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
V
CC2
f
o
) = sum of the outputs.
S
(C
L
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
14-Pin Plastic DIL
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV74 N
74LV74 D
74LV74 DB
74LV74 PW
NORTH AMERICA
74LV74 N
74LV74 D
74LV74 DB
74LV74PW DH
PKG. DWG. #
SOT27-1
SOT108-1
SOT337-1
SOT402-1
PIN DESCRIPTION
PIN
NUMBER
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
SYMBOL
1R
D,
2R
D
1D, 2D
1CP, 2CP
1S
D,
2S
D
1Q, 2Q
1Q
,
2Q
GND
V
CC
FUNCTION
Asynchronous reset-direct input
(active-LOW)
Data inputs
Clock input (LOW-to-HIGH),
edge-triggered)
Asynchronous set-direct input
(active-LOW)
True flip-flop outputs
Complement flip-flop outputs
Ground (0V)
Positive supply voltage
FUNCTION TABLE
INPUTS
S
D
R
D
CP
L
H
X
H
L
X
L
L
X
INPUTS
S
D
H
H
H
L
X
°
Q
n+1
2
=
=
=
=
=
OUTPUTS
D
X
X
X
D
L
H
Q
H
L
H
Q
n+1
L
H
Q
L
H
H
Q
n+1
H
L
OUTPUTS
°
°
R
D
H
H
CP
HIGH voltage level
LOW voltage level
don’t care
LOW-to-HIGH CP transition
state after the next LOW-to-HIGH CP transition
1998 Apr 20
853-1888 19258
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive edge-trigger
74LV74
LOGIC DIAGRAM (ONE FLIP-FLOP)
Q
C
C
C
C
D
C
C
Q
C
R
D
C
S
D
CP
C
C
SV00334
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
Input voltage
Output voltage
Operating ambient temperature range in free
air
Input rise and fall times except for
Schmitt-trigger inputs
See DC and AC
characteristics
V
CC
= 1.0V to 2.0V
V
CC
= 2.0V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V to 5.5V
PARAMETER
DC supply voltage
CONDITIONS
See Note1
MIN
1.0
0
0
–40
–40
–
–
–
–
–
–
–
–
TYP.
3.3
–
–
MAX
5.5
V
CC
V
CC
+85
+125
500
200
100
50
UNIT
V
V
V
°C
t
r
, t
f
ns/V
NOTE:
1. The LV is guaranteed to function down to V
CC
= 1.0V (input levels GND or V
CC
); DC characteristics are guaranteed from V
CC
= 1.2V to V
CC
= 5.5V.
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
,
±I
CC
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC output diode current
DC output source or sink current
– standard outputs
DC V
CC
or GND current for types with
–standard outputs
Storage temperature range
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
V
I
< –0.5 or V
I
> V
CC
+ 0.5V
V
O
< –0.5 or V
O
> V
CC
+ 0.5V
–0.5V < V
O
< V
CC
+ 0.5V
CONDITIONS
RATING
–0.5 to +7.0
20
50
25
50
–65 to +150
750
500
400
UNIT
V
mA
mA
mA
mA
°C
P
t t
tot
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 20
4
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