EP20K200CQ208C7N datasheet, PDF

Datasheet> All Categories > Programmable logic devices> Programmable logic> EP20K200CQ208C7N

EP20K200CQ208C7N: DescriptionLoadable PLD, 1.48ns, PQFP208, 30.40 X 30.40 MM, 0.50 MM PITCH, PLASTIC, QFP-208; CategoryProgrammable logic devices Programmable logic; File Size781KB，94 Pages; ManufacturerAltera (Intel); Environmental Compliance

Download Datasheet Parametric View All

EP20K200CQ208C7N Overview

Loadable PLD, 1.48ns, PQFP208, 30.40 X 30.40 MM, 0.50 MM PITCH, PLASTIC, QFP-208

EP20K200CQ208C7N Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	QFP
package instruction	FQFP,
Contacts	208
Reach Compliance Code	compliant
JESD-30 code	S-PQFP-G208
JESD-609 code	e3
length	28 mm
Humidity sensitivity level	3
Dedicated input times	4
Number of I/O lines	136
Number of terminals	208
Maximum operating temperature	85 °C
Minimum operating temperature
organize	4 DEDICATED INPUTS, 136 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	245
Programmable logic type	LOADABLE PLD
propagation delay	1.48 ns
Certification status	Not Qualified
Maximum seat height	4.1 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
Temperature level	OTHER
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	28 mm
Base Number Matches	1

Preview

Download Datasheet

View All

APEX 20KC

Programmable Logic

Device

Data Sheet

February 2004 ver. 2.2

Features...

■

Programmable logic device (PLD) manufactured using a 0.15-µm all-

layer copper-metal fabrication process

–

25 to 35% faster design performance than APEX

20KE devices

–

Pin-compatible with APEX 20KE devices

–

High-performance, low-power copper interconnect

–

MultiCore

architecture integrating look-up table (LUT) logic

and embedded memory

–

LUT logic used for register-intensive functions

–

Embedded system blocks (ESBs) used to implement memory

functions, including first-in first-out (FIFO) buffers, dual-port

RAM, and content-addressable memory (CAM)

High-density architecture

–

200,000 to 1 million typical gates (see

Table 1)

–

Up to 38,400 logic elements (LEs)

–

Up to 327,680 RAM bits that can be used without reducing

available logic

Note (1)

EP20K400C

1,052,000

400,000

16,640

104

212,992

-7, -8, -9

1,664

488

Table 1. APEX 20KC Device Features

Feature

Maximum system gates

Typical gates

LEs

ESBs

Maximum RAM bits

PLLs

(2)

Speed grades

(3)

Maximum macrocells

Maximum user I/O pins

Notes to

Table 1:

(1)

(2)

(3)

EP20K200C

526,000

200,000

8,320

106,496

-7, -8, -9

832

376

EP20K600C

1,537,000

600,000

24,320

152

311,296

-7, -8, -9

2,432

588

EP20K1000C

1,772,000

1,000,000

38,400

160

327,680

-7, -8, -9

2,560

708

The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to

57,000 additional gates.

PLL: phase-locked loop.

The -7 speed grade provides the fastest performance.

Altera Corporation

DS-APEX20KC-2.2

Recommended Resources

FM demodulation circuit using TA7343

Souyiji mid-amplifier circuit using RC coupling and concentrated filter

Optical toy box circuit

22 commonly used diode single-phase rectifier circuits Figure 1

Electronic ballast circuit 3

555 ventilation fan automatic control circuit

msp430 emulation: I need help. If I use IAR to simulate msp430 and 430 is not encrypted, can I use jtag to read the internal code of msp430 directly? Thank you....; 15075527087 MCU

Serial communication of TI MSP430F5438A: Serial communication is widely used. It outputs the key information of the lower computer to the PC through the serial port. It looks comfortable and convenient to use. It is often used when debugging...; 火辣西米秀 Microcontroller MCU

What do you think Intel's Edison is suitable for?: The Intel Edison module looks quite functional, with a dual-core Quark SOC chip, running the Linux operating system, supporting Wi-Fi and Bluetooth connections, 1G of LPDDR3 RAM and 4G of eMMC flash. ...; dcexpert DIY/Open Source Hardware

Circuit Problem Analysis: As shown in the figure below, the circuit has the following problems:1. The output V1 of the above op amp was tested with a 6.5-digit multimeter. The value dropped at a speed of about 1uV/S in the uV ...; 呜呼哀哉 Analog electronics

Nissan LEAF leads to lower-cost EVs (I): Aims to seize market dominance: Nissan LEAF leads to lower-cost EVs (I): Aims to seize market dominance...; 安_然 Analog electronics

Schematic diagram of a STM32F103ZE development board (powerful): 480 yuan including TFT, high cost performance[align=left][font=宋体][size=10.5pt][font=宋体][size=10.5pt][b]Hardware resources:[/b][/size][/font][/size][/font][/align] [align=left][font=宋体][size=10.5pt][f...; armflyok stm32/stm8

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components