M
PIC16C924
TABLE 1:
COMPARE OUTPUT LOW
SWITCHING
I/O Pin
State
H
L
1000
1001
101x
11xx
H
L
H
L
H
L
H
L
Change CCP to
CCPxM<3:0> =
1001
0xxx
L
L
H
L
—
—
L
L
L
L
1000
L
L
—
—
L
L
L
L
L
L
PIC16C924 Rev. A Silicon/Data Sheet Errata
The PIC16C924 (Rev. A) parts you have received con-
form functionally to the Device Data Sheet
(DS30444E), except for the anomalies described
below.
All the problems listed here will be addressed in future
revisions of the PIC16C924 silicon.
CCP Mode
CCPxM<3:0> =
1. Module: 8-bit A/D Module
If the analog port is configured so that all analog
pins are digital inputs (PCFG2:PCFG0 =
11x),
then doing a conversion on any pin of the analog
port will give a result of ADRES = 0xFF.
Work around
Configure the PCFG2:PCFG0 bits to a value that
has any pin of the analog port configured as an
analog input (such as PCFG2:PCFG0 =
100).
Conversion on any pin of the analog port (analog
or digital) will now convert as expected.
2. Module: CCP (Compare Mode)
The Compare mode may not operate as expected
when configuring the compare match to drive the
I/O pin low (CCPxM<3:0> =
1001).
When the CCP module is changed to compare
output low (CCPxM<3:0> =
1001)
from any other
non-compare CCP mode, the I/O pin will immedi-
ately be driven low, regardless of the state of the
I/O data latch. The pin will remain low when the
compare match occurs (see Table 1).
However, when the CCP module is changed to
compare output high (CCPxM<3:0> =
1000)
from
any other CCP mode, the I/O pin will immediately
be driven low, regardless of the state of the I/O
data latch. The pin will be driven high when the
compare match occurs.
Work around
To have the I/O pin high until the compare match
low occurs, force a compare match high to get the
I/O pin into the high state, then reconfigure the
compare match to force the I/O low when the com-
pare condition occurs.
3. Module: CCP (Compare Mode)
The special event trigger of the Compare mode
may not occur if both of the following conditions
exist:
• An instruction one cycle (T
CY
) prior to a
Timer1/Compare register match has literal
data equal to the address of a CCP register
being used. Specific cases include:
Unit
CCP1
Register
CCPR1L
CCPR1H
CCP1CON
Literal Data
15h
16h
17h
• An instruction in the same cycle as a Timer1/
Compare register match has an MSb of ‘0’.
The interrupt for the compare event will still be
generated, but no special event trigger will occur.
Work around
Use the Interrupt Service Routine instead of using
the special event trigger to reset Timer1 (and start
an A/D conversion, if applicable).
2001 Microchip Technology Inc.
DS80111B-page 1
PIC16C924
4. Module: SSP Module (I
2
C™ Mode)
If the bus is active when the I
2
C mode is enabled,
and the next 8 bits of data on the bus match the
address of the device, then the SSP module will
generate an Acknowledge pulse.
Work around
Before enabling the I
2
C mode, ensure that the bus
is not active.
6. Module: SSP (SPI Mode)
When the SPI is using Timer2/2 as the clock
source, a shorter-than-expected SCK pulse may
occur on the first bit of the transmitted/received
data (see Figure 1).
FIGURE 1:
SCK PULSE VARIATION
USING TIMER 2/2
Write SSPBUF
5. Module: SSP (SPI™ Mode)
The Synchronous Serial Port module in SPI Mas-
ter mode only, allows the transmission of 1 byte of
data at a time. The module must be disabled and
then re-enabled between each byte transmission.
Work around
Once the SSP module has been configured in SPI
Master mode and one byte of data has been trans-
mitted, wait for the interrupt flag bit SSPIF
(PIR1<3>) or BF (SSPSTAT<0>) to be set. This
indicates that the byte of data has been transmit-
ted. Then, disable the SSP by clearing the SSPEN
bit of the SSPCON register. Re-enable the SSP by
setting the SSPEN bit. The SPI module will now
transmit the next data byte written to SSPBUF.
Refer to Example 1 for sample code.
SD0
bit0=1 bit1=0 bit2=1 . . . .
SCK
Work around
To avoid producing the short pulse, turn off Timer2
and clear the TMR2 register, load the SSPBUF
with the data to transmit, and then turn Timer2
back on. Refer to Example 2 for sample code.
EXAMPLE 2:
AVOIDING THE INITIAL
SHORT SCK PULSE
;Bank 1
;Data received?
;(Xmit complete?)
;No
;Bank 0
;W = SSPBUF
;Save in user RAM
;W = TXDATA
;Timer2 off
;Clear Timer2
;Xmit New data
;Timer2 on
EXAMPLE 1:
MOVWF SSPBUF
DISABLING AND
RE-ENABLING THE SSP
;data byte is
;in W register
;change to bank1
;wait for xmit
;buffer to empty
;change to bank0
;disable SSP
;enable SSP
BSF
STATUS, RP0
LOOP BTFSS SSPSTAT, BF
GOTO
BCF
MOVF
MOVWF
MOVF
BCF
CLR
MOVWF
BSF
LOOP
STATUS, RP0
SSPBUF, W
RXDATA
TXDATA, W
T2CON, TMR2ON
TMR2
SSPBUF
T2CON, TMR2ON
WAIT
BSF
STATUS,RP0
BTFSS PIR1, SSPIF
GOTO
BCF
BCF
BSF
WAIT
STATUS,RP0
SSPCON,SSPEN
SSPCON,SSPEN
When the SSP is disabled, the PORTC data latch
value is placed on the pins. The value in bit 3 of
PORTC (SCK) should have the same value as the
idle state of SCK. For example, if the clock idles
high, then bit 3 of PORTC must be set high. If bit
3 of PORTC is not configured the same as the idle
state of the clock, you may experience an addi-
tional clock when the SPI is disabled then re-
enabled.
7. Module: Timer0
The TMR0 register may increment when the WDT
postscaler is switched to the Timer0 prescaler. If
TMR0 = FFh, this will cause TMR0 to overflow
(setting T0IF).
Work around
Follow the following sequence:
a) Read the 8-bit TMR0 register into the
W register.
b) Clear the TMR0 register.
c) Assign WDT postscaler to Timer0.
d) Write W register to TMR0.
DS80111B-page 2
2001 Microchip Technology Inc.
PIC16C924
8. Module: Timer1
The Timer1 value may unexpectedly increment if
either the TMR1H or the TMR1L register is written.
If Timer1 is ON, then turned OFF, performing any
write instruction with TMR1H as the destination
may cause TMR1L to increment.
EXAMPLE 3:
TMR1L INCREMENT
(CASE 1)
BSF T1CON, TMR1ON
:
BCF T1CON, TMR1ON
MOVF TMR1H, 1
TMR1 value before
MOVF
instruction:
TMR1H:TMR1L = 3F:00
TMR1 value after
MOVF
instruction:
TMR1H:TMR1L = 3F:01
EXAMPLE 4:
TMR1L INCREMENT
(CASE 2)
BSF T1CON, TMR1ON
:
BCF T1CON, TMR1ON
MOVF TMR1H, 1
TMR1 value before
MOVF
instruction:
TMR1H:TMR1L = FF:FF
TMR1 value after
MOVF
instruction:
TMR1H:TMR1L = FF:00
If Timer1 is ON, then turned OFF when
TMR1H:TMR1L = xx:FF, performing any write
instruction with TMR1L as the destination may
cause TMR1H to increment.
EXAMPLE 5:
TMR1H INCREMENT
BSF T1CON, TMR1ON
BCF T1CON, TMR1ON
CLRF TMR1L
TMR1 value before
CLRF
instruction:
TMR1H:TMR1L = FF:FF
TMR1 value after
CLRF
instruction:
TMR1H:TMR1L = 00:00
(TMR1IF is
not
set.)
Work around
To preserve Timer1 register values:
a) Read Timer1 register values into “shadow”
registers.
b) Perform any write instruction(s) on the
shadow registers.
c) Write the shadow register values back into
the Timer1 registers.
2001 Microchip Technology Inc.
DS80111B-page 3
PIC16C924
Clarifications/Corrections to the Data Sheet:
In the Device Data Sheet (DS30444E), the following
clarifications and corrections should be noted.
1. Module: I/O Ports
The specification for the High Voltage Open Drain
I/O (the RA4 pin on most devices) cannot be met
without possible long term reliability issues on that
I/O pin. If a high voltage drive is required, use an
external transistor that can support the required
voltage.
TABLE 1:
Param
No.
D150
DC SPECIFICATION CHANGES FROM DATA SHEET
New Specification
Sym.
Characteristic
Min
V
OD
Open Drain High Voltage
—
Typ
—
Max
10
Data Sheet
Specification
Min
—
Typ
—
Max
14
V
Units
2. Module: 8-Bit A/D
The minimum A/D reference voltage has been
improved to the values shown in Table 2.
TABLE 2:
Param
No.
A20
Sym.
DC SPECIFICATION CHANGES FROM DATA SHEET
New Specification
Characteristic
Min
V
REF
Reference Voltage
2.5*
Typ
—
Max
V
DD
+
0.3 V
Min
3.0
Typ
—
Max
V
DD
+
0.3 V
V
Data Sheet Specification
Units
* This parameter is characterized but not tested.
3. Module: SSP (SPI Mode Timing
Specifications)
The SPI interface timings have been modified to
the values shown in Table 2.
TABLE 3:
Param
No.
71
71A
72
72A
73A
DC SPECIFICATION CHANGES FROM DATA SHEET
New Specification
Sym.
Characteristic
Min
T
SC
H SCK input high
Continuous
time (Slave mode)
Single Byte
(1)
T
SC
L SCK input low time Continuous
(Slave mode)
Single Byte
(1)
T
B
2
B
Last clock edge of the Byte1 to 1st
clock edge of the Byte2
(1)
1.25 T
CY
+ 30 ns
40
1.25 T
CY
+ 30 ns
40
1.5 T
CY
+ 40 ns
Typ
—
—
—
—
—
Max
—
—
—
—
—
T
CY
+ 20
ns
Data Sheet
Specification
Min
T
CY
+ 20
ns
Typ
—
N.A.
—
N.A.
N.A.
—
Max
—
ns
ns
ns
ns
ns
Units
* This parameter is characterized but not tested.
Note 1:
Specification 73A is only required if specifications 71A and 72A are used.
DS80111B-page 4
2001 Microchip Technology Inc.
PIC16C924
4. Module: Timer1
The operation of Timer1 needs some clarification
when the timer registers are written and the
TMR1ON bit is set.
The internal clock signal that is the input to the
TMR1 prescaler affects the incrementing of Timer1
(TMR1H:TMR1L registers and the Timer1 pres-
caler). When the Timer1 registers are NOT written,
the Timer1 will increment on the rising edge of the
TMR1 increment clock.
When the TMR1H and/or TMR1L registers are
written while this clock is high, TMR1 will incre-
ment on the next rising edge of this clock.
When the TMR1H and/or TMR1L registers are
written while this clock is low, TMR1 will not incre-
ment on the next rising edge of this clock, but must
first have a falling clock and then the rising clock
for TMR1 to increment.
Figure 1 shows the two cases of writes to the
TMR1H and/or TMR1L registers. Due to the V
IH
and V
IL
thresholds on the oscillator/clock pins,
external Timer1 oscillator components, and exter-
nal clock frequency, the Timer1 increment clock
may not be of a 50% duty cycle.
The TMR1 increment clock is out of phase of the
T1OSO/T1CKI pin by a small propagation delay.
FIGURE 1:
WRITES TO TIMER1 (EXTERNAL CLOCK / OSCILLATOR MODE)
TMR1 Increment
Clock (Input to Prescaler)
Write to TMR1H and/or TMR1L Register(s)
Write to TMR1H and/or TMR1L Register(s)
TMR1H:TMR1L Increments
TMR1H:TMR1L Increments
5. Module: I/O Ports
The block diagram for PORTC presented in
Figure 5-5 of the Device Data Sheet (DS30444E)
is incorrect. The correct block diagram is shown in
Figure 2.
FIGURE 2:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
Port/Peripheral Select
(2)
Peripheral Data Out
Data Bus
D
Q
WR
Port
CK Q
Data Latch
WR
TRIS
D
CK
Q
Q
N
V
SS
Peripheral
OE
(3)
RD TRIS
Q
RD
Port
Peripheral Input
D
EN
Schmitt
Trigger
I/O
pin
(1)
0
1
V
DD
P
TRIS Latch
Note 1:
I/O pins have diode protection to V
DD
and V
SS
.
2:
Port/Peripheral select signal selects between
port data and peripheral output.
3:
Peripheral OE (output enable) is only activated if
peripheral select is active.
2001 Microchip Technology Inc.
DS80111B-page 5
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