INTEGRATED CIRCUITS
SC26C92
Dual universal asynchronous
receiver/transmitter (DUART)
Product specification
Supersedes data of 1998 Nov 09
IC19 Data Handbook
2000 Jan 31
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual universal asynchronous receiver/transmitter (DUART)
SC26C92
DESCRIPTION
The SC26C92 is a pin and function replacement for the SCC2692
and SCN2681 with added features and deeper FIFOs. Its
configuration on power up is that of the 2692. Its differences from
the 2692 are: 8 character receiver, 8 character transmit FIFOs,
watch dog timer for each receiver, mode register 0 is added,
extended baud rate and overall faster speeds, programmable
receiver and transmitter interrupts. (The SCC2692 is not being
discontinued.)
The Philips Semiconductors SC26C92 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
CMOS-LSI communications device that provides two full-duplex
asynchronous receiver/transmitter channels in a single package. It
interfaces directly with microprocessors and may be used in a polled
or interrupt driven system and provides modem and DMA interface.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of 27 fixed baud
rates, a 16X clock derived from a programmable counter/timer, or an
external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver and transmitter is buffered by eight character FIFOs
to minimize the potential of receiver overrun, transmitter underrun
and to reduce interrupt overhead in interrupt driven systems. In
addition, a flow control capability is provided via RTS/CTS signaling
to disable a remote transmitter when the receiver buffer is full.
Also provided on the SC26C92 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
The SC26C92 is available in three package versions: 40-pin 0.6”
wide DIP, a 44-pin PLCC and 44–pin plastic quad flat pack (PQFP).
•
Programmable baud rate for each receiver and transmitter
selectable from:
–
27 fixed rates: 50 to 230.4k baud
–
Other baud rates to 230.4k baud at 16X
–
Programmable user-defined rates derived from a
programmable counter/timer
–
External 1X or 16X clock
•
Parity, framing, and overrun error detection
•
False start bit detection
•
Line break detection and generation
•
Programmable channel mode
–
Normal (full-duplex)
–
Automatic echo
–
Local loopback
–
Remote loopback
–
Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
•
Multi-function 7-bit input port
–
Can serve as clock, modem, or control inputs
–
Change of state detection on four inputs
–
Inputs have typically >100k pull-up resistors
•
Multi-function 8-bit output port
–
Individual bit set/reset capability
–
Outputs can be programmed to be status/interrupt signals
–
FIFO states for DMA and modem interface
•
Versatile interrupt system
–
Single interrupt output with eight maskable interrupting
conditions
–
Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
–
Each FIFO can be programmed for four different interrupt levels
–
Watch dog timer for each receiver
FEATURES
•
Maximum data transfer rates:
1X – 1Mb/sec, 16X – 1Mb/sec
•
Dual full-duplex independent asynchronous receiver/transmitters
•
8 character FIFOs for each receiver and transmitter
•
Programmable data format
–
5 to 8 data bits plus parity
–
Odd, even, no parity or force parity
–
1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•
16-bit programmable Counter/Timer
•
Automatic wake-up mode for multidrop applications
•
Start-end break interrupt/status
•
Detects break which originates in the middle of a character
•
On-chip crystal oscillator
•
Power down mode
•
Receiver timeout mode
•
Single +5V power supply
•
Powers up to emulate SCC2692
ORDERING INFORMATION
DESCRIPTION
40-Pin Plastic Dual In-Line Package (DIP)
44-Pin Plastic Leaded Chip Carrier (PLCC)
44–Pin Plastic Quad Flat Pack (PQFP)
COMMERCIAL
1
V
CC
= +5V
±10%,
T
A
= 0 to +70°C
SC26C92C1N
SC26C92C1A
SC26C92C1B
INDUSTRIAL
V
CC
= +5V
±10%,
T
A
= -40 to +85°C
SC26C92A1N
SC26C92A1A
SC26C92A1B
DWG #
SOT129-1
SOT187-2
SOT307–2
2000 Jan 31
2
853–1585 23061
Philips Semiconductors
Product specification
Dual universal asynchronous receiver/transmitter (DUART)
SC26C92
NOTE:
1. Commercial devices are tested for the –40 to +85_C.
PIN CONFIGURATIONS
A0
IP3
A1
IP1
A2
A3
IP0
WRN
1
2
3
4
5
6
7
8
40 V
CC
39 IP4
38 IP5
37 IP6
36 IP2
35 CEN
34 RESET
33 X2
32 X1/CLK
31 RxDA
DIP
30 TxDA
29 OP0
28 OP2
27 OP4
26 OP6
25 D0
24 D2
23 D4
22 D6
21 INTRN
PIN/FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A3
IP0
WRN
RDN
RxDB
TxDB
OP1
OP3
OP5
OP7
N/C
D1
D3
D5
D7
GND
GND
INTRN
D6
D4
D2
D0
PIN/FUNCTION
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
N/C
OP6
OP4
OP2
OP0
TxDA
RxDA
X1/CLK
X2
RESET
CEN
IP2
IP6
IP5
IP4
V
CC
V
CC
A0
IP3
A1
IP1
A2
11
12
TOP VIEW
22
23
PQFP
1
44
34
33
INDEX
CORNER
7
6
1
40
39
PLCC
17
18
TOP VIEW
28
29
RDN 9
RxDB 10
TxDB 11
OP1 12
OP3 13
OP5 14
OP7 15
D1 16
D3 17
D5 18
D7 19
V
SS
20
PIN/FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A0
IP3
A1
IP1
A2
A3
IP0
WRN
RDN
RXDB
NC
TXDB
OP1
OP3
OP5
OP7
D1
D3
D5
D7
V
SS
PIN/FUNCTION
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
INTRN
D6
D4
D2
D0
OP6
OP4
OP2
OP0
TXDA
NC
RXDA
X1/CLK
X2
RESET
CEN
IP2
IP6
IP5
IP4
V
CC
SD00667
Figure 1. Pin Configurations
2000 Jan 31
3
Philips Semiconductors
Product specification
Dual universal asynchronous receiver/transmitter (DUART)
SC26C92
BLOCK DIAGRAM
8
D0–D7
BUS BUFFER
CHANNEL A
8 BYTE TRANSMIT
FIFO
TRANSMIT
SHIFT REGISTER
TxDA
RDN
WRN
CEN
A0–A3
RESET
4
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
8 BYTE RECEIVE
FIFO
WATCH DOG TIMER
RECEIVE SHIFT
REGISTER
MRA0, 1, 2
CRA
SRA
RxDA
INTERRUPT CONTROL
INTRN
IMR
ISR
CHANNEL B
(AS ABOVE)
TxDB
RxDB
INTERNAL DATABUS
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
IPCR
ACR
CONTROL
TIMING
BAUD RATE
GENERATOR
TIMING
7
IP0-IP6
CLOCK
SELECTORS
COUNTER/
TIMER
OUTPUT PORT
FUNCTION
SELECT LOGIC
8
X1/CLK
XTAL OSC
X2
CSRA
CSRB
ACR
U
CTPL
CTPL
OP0-OP7
OPCR
OPR
V
CC
V
SS
SD00153
Figure 2. Block Diagram
2000 Jan 31
4
Philips Semiconductors
Product specification
Dual universal asynchronous receiver/transmitter (DUART)
SC26C92
PIN DESCRIPTION
SYMBOL
D0-D7
CEN
PKG
40,44
X
X
PIN
TYPE
I/O
I
NAME AND FUNCTION
Data Bus:
Bidirectional 3-State data bus used to transfer commands, data and status between the DUART
and the CPU. D0 is the least significant bit.
Chip Enable:
Active-Low input signal. When Low, data transfers between the CPU and the DUART are
enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the D0-D7 lines
in the 3-State condition.
Write Strobe:
When Low and CEN is also Low, the contents of the data bus is loaded into the addressed
register. The transfer occurs on the rising edge of the signal.
Read Strobe:
When Low and CEN is also Low, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
Address Inputs:
Select the DUART internal registers and ports for read/write operations.
Reset:
A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in the
High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA and
TxDB outputs in the mark (High) state. Sets MR pointer to MR1 and resets MR0.
Interrupt Request:
Active-Low, open-drain, output which signals the CPU that one or more of the eight
maskable interrupting conditions are true. Requires a pullup resistor.
Crystal 1:
Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
Crystal 2:
Crystal connection. See Figure 7. If a crystal is not used this pin must be left open or not driving
more than one TTL equivalent load.
Channel A Receiver Serial Data Input:
The least significant bit is received first. “Mark” is High, “space” is Low.
Channel B Receiver Serial Data Input:
The least significant bit is received first. “Mark” is High, “space” is Low.
Channel A Transmitter Serial Data Output:
The least significant bit is transmitted first. This output is held
in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback mode.
“Mark” is High, “space” is Low.
Channel B Transmitter Serial Data Output:
The least significant bit is transmitted first. This output is
held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode.
‘Mark’ is High, ‘space’ is Low.
Output 0:
General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 1:
General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
Output 2:
General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver
1X clock output.
Output 3:
General purpose output or open-drain, active-Low counter/timer output or Channel B transmitter
1X clock output, or Channel B receiver 1X clock output.
Output 4:
General purpose output or Channel A open-drain, active-Low, RxA interrupt ISR[1] output.
Output 5:
General purpose output or Channel B open-drain, active-Low, RxB interrupt ISR[5] output.
Output 6:
General purpose output or Channel A open-drain, active-Low, TxA interrupt ISR[0] output.
Output 7:
General purpose output, or Channel B open-drain, active-Low, TxB interrupt ISR[4] output.
Input 0:
General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an internal
V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 1:
General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an internal
V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 2:
General purpose input or counter/timer external clock input. Pin has an internal V
CC
pull-up device
supplying 1 to 4
mA
of current.
Input 3:
General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 4:
General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 5:
General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Input 6:
General purpose input or Channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
mA
of current.
Power Supply:
+5V supply input.
Ground
WRN
RDN
A0-A3
RESET
X
X
X
X
I
I
I
I
INTRN
X1/CLK
X2
RxDA
RxDB
TxDA
X
X
X
X
X
X
O
I
I
I
I
O
TxDB
X
O
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
IP3
X
X
X
X
X
X
X
X
X
X
X
X
O
O
O
O
O
O
O
O
I
I
I
I
IP4
X
I
IP5
X
I
IP6
X
I
V
CC
GND
X
X
I
I
2000 Jan 31
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