DS87C530/DS83C530
EPROM/ROM Microcontrollers with
Real-Time Clock
www.maxim-ic.com
FEATURES
80C52 Compatible
8051 Instruction-Set Compatible
Four 8-Bit I/O Ports
Three 16-Bit Timer/Counters
256 Bytes Scratchpad RAM
Large On-Chip Memory
16kB EPROM (OTP)
1kB Extra On-Chip SRAM for MOVX
ROMSIZE Features
Selects Effective On-Chip ROM Size from
0 to 16kB
Allows Access to Entire External Memory Map
Dynamically Adjustable by Software
Useful as Boot Block for External Flash
Nonvolatile Functions
On-Chip Real-Time Clock with Alarm Interrupt
Battery Backup Support of 1kB SRAM
High-Speed Architecture
4 Clocks/Machine Cycle (8051 = 12)
Runs DC to 33MHz Clock Rates
Single-Cycle Instruction in 121ns
Dual Data Pointer
Optional Variable Length MOVX to Access
Fast/Slow RAM /Peripherals
Power Management Mode
Programmable Clock Source Saves Power
Runs from (crystal/64) or (crystal/1024)
Provides Automatic Hardware and Software Exit
EMI Reduction Mode Disables ALE
Two Full-Duplex Hardware Serial Ports
High Integration Controller Includes:
Power-Fail Reset
Early-Warning Power-Fail Interrupt
Programmable Watchdog Timer
14 Total Interrupt Sources with Six External
PIN CONFIGURATIONS
TOP VIEW
7
8
1
47
46
DALLAS
DS87C530
DS83C530
20
21
33
34
PLCC, WINDOWED CLCC
39
27
40
26
DALLAS
DS87C530
DS83C530
52
14
1
13
TQFP
The
High-Speed Microcontroller User’s Guide
must
be used in conjunction with this data sheet. Download it
at:
www.maxim-ic.com/microcontrollers
.
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 071107
DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
ORDERING INFORMATION
PART
DS87C530-QCL
DS87C530-QCL+
DS87C530-QNL
DS87C530-QNL+
DS87C530-KCL*
DS87C530-ECL
DS87C530-ECL+
DS87C530-ENL
DS87C530-ENL+
DS83C530-QCL
DS83C530-QCL+
DS83C530-QNL
DS83C530-QNL+
DS83C530-ECL
DS83C530-ECL+
DS83C530-ENL
DS83C530-ENL+
TEMP RANGE
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
0C to +70C
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
0C to +70C
0C to +70C
-40C to +85C
-40C to +85C
MAX CLOCK
SPEED
(MHz)
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
PIN-PACKAGE
52 PLCC
52 PLCC
52 PLCC
52 PLCC
52 Windowed CLCC
52 TQFP
52 TQFP
52 TQFP
52 TQFP
52 PLCC
52 PLCC
52 PLCC
52 PLCC
52 TQFP
52 TQFP
52 TQFP
52 TQFP
+
Denotes a lead(Pb)-free/RoHS-compliant device.
*
The windowed ceramic LCC package is intrinsically lead(Pb) free.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
DETAILED DESCRIPTION
The DS87C530/DS83C530 EPROM/ROM microcontrollers with a real-time clock (RTC) are 8051-
compatible microcontrollers based on the Dallas Semiconductor high-speed core. They use 4 clocks per
instruction cycle instead of the 12 used by the standard 8051. They also provide a unique mix of
peripherals not widely available on other processors. They include an on-chip RTC and battery backup
support for an on-chip 1k x 8 SRAM. The new Power Management Mode allows software to select
reduced power operation while still processing.
A combination of high-performance microcontroller core, RTC, battery-backed SRAM, and power
management makes the DS87C530/DS83C530 ideal for instruments and portable applications. They also
provide several peripherals found on other Dallas high-speed microcontrollers. These include two
independent serial ports, two data pointers, on-chip power monitor with brownout detection and a
watchdog timer.
Power Management Mode (PMM) allows software to select a slower CPU clock. While default operation
uses four clocks per machine cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. There is a
corresponding drop in power consumption when the processor slows.
The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE
signal when it is unneeded.
The DS83C530 is a factory mask ROM version of the DS87C530 designed for high-volume, cost-
sensitive applications. It is identical in all respects to the DS87C530, except that the 16kB of EPROM is
replaced by a user-supplied application program. All references to features of the DS87C530 will apply to
the DS83C530, with the exception of EPROM-specific features where noted. Please contact your local
Dallas Semiconductor sales representative for ordering information.
Note:
The DS87C530/DS83C530 are monolithic devices. A user must supply an external battery or super
cap and a 32.768kHz timekeeping crystal to have permanently powered timekeeping or nonvolatile RAM.
The DS87C530/DS83C530 provide all the support and switching circuitry needed to manage these
resources.
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
Figure 1. Block Diagram
DS87C530/
DS83C530
PIN DESCRIPTION
PIN
PLCC
52
1, 25
29
26
12
TQFP
45
18, 46
22
19
5
NAME
V
CC
GND
V
CC2
GND2
RST
+5V Processor Power Supply
Processor Digital Circuit Ground
+5V RTC Supply.
V
CC2
is isolated from V
CC
to isolate the RTC from digital noise.
RTC Circuit Ground
Reset Input.
This pin contains a Schmitt voltage input to recognize external active
high reset inputs. The pin also employs an internal pulldown resistor to allow for a
combination of wired OR external reset sources. An RC is not required for power-up,
as the device provides this function internally.
Crystal Oscillator Pins.
XTAL1 and XTAL2 provide support for parallel-resonant,
AT-cut crystals. XTAL1 acts also as an input if there is an external clock source in
place of a crystal. XTAL2 is the output of the crystal amplifier.
FUNCTION
23
24
16
17
XTAL2
XTAL1
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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
PIN DESCRIPTION (continued)
PIN
PLCC
38
TQFP
31
NAME
PSEN
FUNCTION
Program Store-Enable Output.
This active-low signal is a chip enable for optional
external ROM memory.
PSEN
provides an active-low pulse and is driven high when
external ROM is not being accessed.
Address Latch-Enable Output.
This pin latches the external address LSB from the
multiplexed address/data bus on Port 0. This signal is commonly connected to the
latch enable of an external 373 family transparent latch. ALE has a pulse width of
1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the
device is in a Reset condition. ALE can be disabled and forced high by writing
ALEOFF = 1 (PMR.2). ALE operates independently of ALEOFF during external
memory accesses.
Port 0 (AD0–AD7), I/O.
Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an
alternate function Port 0 can function as the multiplexed address/data bus to access
off-chip memory. During the time when ALE is high, the LSB of a memory address
is presented. When ALE falls to a logic 0, the port transitions to a bidirectional data
bus. This bus is used to read external ROM and read/ write external RAM memory
or peripherals. When used as a memory bus, the port provides active high drivers.
The reset condition of Port 0 is tri-state. Pullup resistors are required when using
Port 0 as an I/O port.
39
32
ALE
50
49
48
47
46
45
44
43
3
4
5
6
7
43
42
41
40
39
38
37
36
48
49
50
51
52
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
P1.0
P1.1
P1.2
P1.3
P1.4
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate
T2
T2EX
RXD1
TXD1
INT2
INT3
INT4
INT5
Function
External I/O for Timer/Counter 2
Timer/Counter 2 Capture/Reload Trigger
Serial Port 1 Input
Serial Port 1 Output
External Interrupt 2 (Positive Edge Detect)
External Interrupt 3 (Negative Edge Detect)
External Interrupt 4 (Positive Edge Detect)
External Interrupt 5 (Negative Edge Detect)
Port 1, I/O.
Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate
functional interface for Timer 2 I/O, new External Interrupts, and new Serial Port 1.
The reset condition of Port 1 is with all bits at a logic 1. In this state, a weak pullup
holds the port high. This condition also serves as an input mode, since any external
circuit that writes to the port will overcome the weak pullup. When software writes a
0 to any port pin, the device will activate a strong pulldown that remains on until
either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will
cause a strong transition driver to turn on, followed by a weaker sustaining pullup.
Once the momentary strong driver turns off, the port again becomes the output high
(and input) state. The alternate modes of Port 1 are outlined as follows.
8
9
10
1
2
3
P1.5
P1.6
P1.7
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