ZL9117MIRZ-T datasheet, PDF - EEWORLD Datasheet

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Digital DC/DC PMBus 17A Module

ZL9117M

The ZL9117M is a 17A, variable output, step-down

PMBus-compliant digital power supply. Included in the module

is a high-performance digital PWM controller, power MOSFETs,

an inductor, and all the passive components required for a

highly integrated DC/DC power solution. This power module

has built-in auto-compensation algorithms, which eliminates

the need for manual compensation design work. The ZL9117M

operates over a wide input voltage range and supports an

output voltage range of 0.6V to 3.6V, which can be set by

external resistors or via PMBus. This high-efficiency power

module is capable of delivering 17A. Only bulk input and

output capacitors are needed to finish the design. The output

voltage can be precisely regulated to as low as 0.6V with ±1%

output voltage regulation over line, load, and temperature

variations.

The ZL9117M features auto-compensation, internal soft-start,

auto-recovery overcurrent protection, an enable option, and

pre-biased output start-up capabilities.

The ZL9117M is packaged in a thermally enhanced, compact

(15mmx15mm) and low profile (3.5mm) over-molded QFN

package module suitable for automated assembly by standard

surface mount equipment. The ZL9117M is Pb-free and RoHS

compliant.

Figure 1 represents a typical implementation of the ZL9117M.

For PMBus operation, it is recommended to tie the Enable pin

(EN) to SGND.

Features

• Complete digital switch mode power supply

• Fast transient response

• Auto compensating PID filter

• External synchronization

• Output voltage tracking

• Current sharing

• Programmable soft-start delay and ramp

• Overcurrent/undercurrent protection

• PMBus compliant

Applications

• Server, telecom, and datacom

• Industrial and medical equipment

• General purpose point of load

Related Literature

• See

AN2033,

“Zilker Labs PMBus Command Set for DDC

Products”

• See

AN2034,

“Configuring Current Sharing on the ZL2004

and ZL2006”

V

DRV

4.5V TO 6.5V

10µF

16V

4.7µF

16V

4.7µF

16V

10µF

16V

V

IN

4.5V TO 13.2V

CIN

VDRV

VDD

VIN

(EPAD)

VOUT

(EPAD)

ZL9117M

DDC

SCL

I

2

C/SMBus

SDA

SGND

VTRK

VSET

FB+

SA

R

SA

R

SET

FB-

PGND

(EPAD)

RTN

SW

(EPAD)

COUT

VR

V25

POWER GOOD OUTPUT

ENABLE

EXT SYNC

DDC BUS

PG

EN

V

OUT

SYNC

FIGURE 1. A COMPLETE DIGITAL SWITCH MODE POWER SUPPLY, ONLY BULK INPUT AND OUTPUT CAPACITORS ARE REQUIRED TO FINISH THE

DESIGN

July 22, 2013

FN7914.3

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

|

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ZL9117M

Pin Configuration

ZL9117M

(21 LD QFN)

TOP VIEW

SGND

SYNC

DDC

SCL

PG

VR

EN

SA

9

PGND

V25

VDD

10

11

12

8

7

6

5

4

3

2

1

21

20

19

SDA

VSET

VTRK

FB+

VDRV

13

18

FB-

SW

14

VIN

15

PGND

16

VOUT

17

Pin Descriptions

1

2

3

4

5

6

7

8

9

10

11

12

13

14 (epad)

15 (epad)

16 (epad)

17 (epad)

18

19

20

21

LABEL

SDA

SCL

SA

SYNC

PG

EN

DDC

VR

SGND

PGND

V25

VDD

VDRV

SW

VIN

PGND

VOUT

FB-

FB+

VTRK

VSET

TYPE

I/O

I

I/O

O

I

I/O

PWR

I

DESCRIPTION

Serial data. A pull-up resistor is required for this application.

Serial clock. A pull-up resistor is required for this application.

Serial address select pin. Used to assign unique SMBus address to each module.

Clock synchronization. Used for synchronization to external frequency reference.

Power-good output.

Enable input (factory setting active high). Pull-up to enable PWM switching and pull-down to disable PWM switching.

Digital-DC bus (open drain). Interoperability between Zilker Labs modules. A pull-up resistor is required for this

application.

Internal 5V reference used to power internal drivers. Connect 4.7μF bypass capacitor to this pin.

Signal ground. Connect to low impedance ground plane.

Power ground. Connect to low impedance ground plane.

Internal 2.5V reference used to power internal circuitry. Connect 4.7μF bypass capacitor to this pin.

Input supply voltage for controller. Connect 4.7μF bypass capacitor to this pin.

Power supply for internal FET drivers. Connect 10μF bypass capacitor to this pin.

Drive train switch node.

Power supply input FET voltage.

Power ground. Connect to low impedance ground plane.

Power supply output voltage. Output voltage from PWM.

Output voltage feedback. Connect to load return of ground regulation point.

Output voltage feedback. Connect to output regulation point.

Tracking sense input. Used to track an external voltage source.

Output voltage selection pin. Used to set V

OUT

set point and V

OUT

max.

2

FN7914.3

July 22, 2013

ZL9117M

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

ZL9117MIRZ

ZL9117MAIRZ

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to

TB347

for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for

ZL9117M.

For more information on MSL please see Tech Brief

TB363.

PART

MARKING

ZL9117M

ZL9117MA

TEMP RANGE

(°C)

-40 to +85

PACKAGE

(Pb-Free)

21 Ld 15x15 QFN

PKG.

DWG. #

L21.15x15

ZL

DIGITAL MODULE DESIGNATOR

BASE PART NUMBER

FIRMWARE REVISION

BLANK: FC04

A: FC05

xxxxM

F

T

R

Z

S

SHIPPING OPTION

BLANK: BULK

T: TAPE AND REEL

PB‐FREE OPTION

Z: PB‐FREE PRODUCT

OPERATING TEMPERATURE

I: INDUSTRIAL (‐ 40°C TO +85°C)

PACKAGE DESIGNATOR

R: QUAD FLAT NO‐LEAD (QFN)

Firmware Revision History

Firmware Revision Code

FC04

FC05

1. Bug fixed to clear VMON_UV_WARNING when VMON (VDRV)

voltage is ramped up with a delayed of >50ms from VIN.

2. Make OVUV_CONFIG = 0x00 a factory default.

3. Make DEADTIME = 1410 Freeze a factory default.

Change Description

Note

Not recommended for a new design.

Recommended for a new design.

3

FN7914.3

July 22, 2013

ZL9117M

ZL9117M Internal Block Diagram

FB

VDRV

VIN

VDD

VTRK

VSET

PG

SS

MGN

EN

LDO

OV/UV POWER MANAGEMENT

OC/UC

CURRENT SHARE

INTERLEAVE

AUTOCOMP

VDRV

GATE DRIVE LOGIC

SYNC

OUT

V25

VR

GH

PWMH

BST

PWML

SW

0.22µH

SW

SYNC

PLL

D-PWM

VOUT

NVM

GL

GND

SUPERVISOR

NLR

DIGITAL

COMPENSATOR

POWER STAGE

GATE DRIVER

PROTECTION

CSA

22

SCL

SDA

DDC

SA

ADC

TEMP

SENSOR

SGND

DGND

DIGITAL CONTROLLER

PGND

SGND

COMMUNICATION

VDD

VDRV

ADC

VSA

22

FB-

FB+

4

FN7914.3

July 22, 2013

ZL9117M

Typical Application - Single Module

V

IN

4.5 to 13.2V

330µF

BULK

C

1

+

2X22µF

CERAMIC

C

2

VIN

V

DD

4.5 to 13.2V

10µF

CERAMIC

VDD

C

3

10µF

CERAMIC

VDRV

ZL9117M

SCL

SDA

DDC

EN

PGND

SYNC

R

SA

= 51.1k

Ω

SMBUS ADD = 0X2A

SGND

VSET

VTRK

SA

FB+

FB-

R

4

= 200

Ω

4X100µF

CERAMIC

VOUT

C

7

2x330µF

POSCAP

C

8

+

V

OUT

1.2V 17A

V25

C

6

VR

C

5

4.7µF

CERAMIC

V

DRV

4.5 to 6.5V

C

4

V

LOGIC

10k

Ω

10k

Ω

4.75k

Ω

3.0 to 6.0V

R

1

SCL

SDA

DDC

EN

VTRK

SYNC

R

2

R

3

4.7µF

CERAMIC

R

SET

= 31.6k

Ω

V

OUT

= 1.2V

NOTES:

4. R

1

and R

2

are not required if the PMBus host already has I

2

C pull-up resistors.

5. Only one R

3

per DDC bus is required when DDC bus is shared with other modules.

6. The VR, V25, VDRV, and VDD capacitors should be placed no farther than 0.5cm from the pin.

7. R

4

is optional but recommended to sink possible ~100µA backflow current from the FB+ pin. Backflow current is present only when the module is

in a disabled state with power still available at the V

DD

pin.

8. When Low-Side power FET is selected to be enabled as a response to an OV fault, it is recommended to place a Schottky diode close to the VOUT and

PGND pins in order to prevent voltage at the FB+ pin dropping below absolute minimum of -0.3V, which may be caused by negative current build up

on the internal power inductor.

5

FN7914.3

July 22, 2013

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