2-Axis Compass with Algorithms
HMC6352
The Honeywell HMC6352 is a fully integrated compass module that
combines 2-axis magneto-resistive sensors with the required analog and
digital support circuits, microprocessor and algorithms for heading
computation. By combining the sensor elements, processing electronics,
and firmware in to a 6.5mm by 6.5mm by 1.5mm LCC package,
Honeywell offers a complete, ready to use electronic compass. This
provides design engineers with the simplest solution to integrate high
volume, cost effective compasses into wireless consumer electronics,
vehicle compassing, and antenna positioning.
Honeywell continues to maintain product excellence and performance by
introducing innovative solid-state magnetic sensor solutions. These are highly reliable, top performance products that are
delivered when promised. Honeywell’s magnetic sensor products provide real solutions you can count on.
FEATURES
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Compass with Heading Output
Full Integration of 2-Axis Magnetic
Sensors and Electronics
Compass Algorithms
Small Surface Mount Package
(6.5 x 6.5 x 1.5mm, 24-pin LCC)
Low Voltage Operation (2.7 to 5.2V )
I C 2-Wire Serial Interface
Lead Free Package Construction
Wide Magnetic Field Range (± 2 Oe)
Set/Reset Strap Drive
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BENEFITS
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A complete compass solution including compass firmware
complete
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A chip-scaledigital compass solution with heading angle output in a
package.
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For computation of heading, and magnetic calibration for hard-iron.
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Small size, easy to assemble and compatible with high speed SMT
assembly
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Compatible with battery powered applications
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Works as a Slave to Customer’s Master Processor (100kHz).
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Complies with Current Environmental Standards (RoHS)
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Sensor Can Be Used in Strong Magnetic Field Environments
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Stray Magnetic Field Protection and Temperature Compensation
HMC6352
SPECIFICATIONS
Characteristics
Supply Voltage
Supply Current
Conditions
(1)
Min
2.7
Typ
3.0
1
1
2
Max
5.2
Units
Volts
µA
mA
Vsupply to GND
Vsupply to GND
Sleep Mode (Vsupply = 3.0V)
Steady State (Vsupply = 3.0V)
Steady State (Vsupply = 5.0V)
Dynamic Peaks
10
0.75
mA
mA
gauss
degRMS
deg
deg
gauss
Field Range
(2)
Total applied field
HMC6352
0.10
-
2.5
0.5
1.0
Heading Accuracy
Heading Resolution
Heading Repeatability
Disturbing Field
Max. Exposed
Field
Operating Temperature
Storage Temperature
Peak Reflow Temperature
Moisture Sensivity
Output
Size
Sensitivity starts to degrade. Enable
set/reset function to restore sensitivity.
No permanent damage and set/reset
function restores performance.
Ambient
Ambient
For Lead-Free SMT Reflow
Max 240°C
Heading, Mag X, Mag Y
6.5 x 6.5 x 1.5
20
10000
-20
-55
230
-
MSL3
70
125
240
gauss
°C
°C
°C
-
mm
grams
Weight
0.14
(1) Tested at 25°C except stated otherwise.
(2) Field upper limit can be extended by using external resistors across CA1/CA2 and CB1/CB2.
PIN CONFIGURATION/PACKAGE DIMENSIONS
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HMC6352
PIN DESCRIPTIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
OF-
SR+
NC
_MCLR
GND
NC
SDI
SDO
PGM
SCL
SS
NC
NC
VDD
NC
NC
NC
NC
CB2
CB1
NC
CA2
CA1
OF+
Description
No User Connection (Offset Strap Negative)
No User Connection (Set/Reset Strap Positive)
No User Connection
Master Clear Input
Supply/System Ground
No User Connection
I2C Data Output (SPI Data In)
No User Connection (SPI Data Out)
No User Connection (Program Enable)
I2C Clock (SPI Clock)
No User Connection (Slave Select)
No User Connection
No User Connection
Supply Voltage Positive Input (+2.7VDC to +5.0VDC)
No User Connection
No User Connection
No User Connection
No User Connection
Amplifier B Filter Capacitor Connection
Amplifier B Filter Capacitor Connection
No User Connection
Amplifier A Filter Capacitor Connection
Amplifier A Filter Capacitor Connection
No User Connection (Offset Strap Positive)
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C COMMUNICATION PROTOCOL
The HMC6352 communicates via a two-wire I C bus system as a slave device. The HMC6352 uses a layered protocol
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with the interface protocol defined by the I C bus specification, and the lower command protocol defined by Honeywell.
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The data rate is the standard-mode 100kbps rate as defined in the I C Bus Specification 2.1. The bus bit format is an 8-bit
Data/Address send and a 1
-bit acknowledge bit. The format of the data bytes (payload) shall be case sensitive ASCII
characters or binary data to the HMC6352 slave, and binary data returned. Negative binary values will be in two’s
complement form. The default (factory) HMC6352 7-bit slave address is 42(hex) for write operations, or 43(hex) for read
operations.
The HMC6352 Serial Clock (SCL) and Serial Data (SDA) lines do not have internal pull-up resistors, and require resistive
pull-ups (Rp) between the master device (usually a host microprocessor) and the HMC6352. Pull-up resistance values of
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about 10k ohms are recommended with a nominal 3.0-volt supply voltage. Other values may be used as defined in the I C
Bus Specification 2.1.
The SCL and SDA lines in this bus specification can be connected to a host of devices. The bus can be a single master to
multiple slaves, or it can be a multiple master configuration. All data transfers are initiated by the master device which is
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responsible for generating the clock signal, and the data transfers are 8 bit long. All devices are addressed by I C’s
th
unique 7 bit address. After each 8-bit transfer, the master device generates a 9 clock pulse, and releases the SDA line.
The receiving device (addressed slave) will pull the SDA line low to acknowledge (ACK) the successful transfer or leave
the SDA high to negative acknowledge (NACK).
Per the I C spec, all transitions in the SDA line must occur when SCL is low. This requirement leads to two unique
conditions on the bus associated with the SDA transitions when SCL is high. Master device pulling the SDA line low while
the SCL line is high indicates the Start (S) condition, and the Stop (P) condition is when the SDA line is pulled high while
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the SCL line is high. The I C protocol also allows for the Restart condition in which the master device issues a second
start condition without issuing a stop.
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HMC6352
All bus transactions begin with the master device issuing the start sequence followed by the slave address byte. The
address byte contains the slave address; the upper 7 bits (bits7-1), and the Least Significant bit (LSb). The LSb of the
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address byte designates if the operation is a read (LSb=1) or a write (LSb=0). At the 9 clock pulse, the recieving slave
device will issue the ACK (or NACK). Following these bus events, the master will send data bytes for a write operation, or
the slave will transmit back data for a read operation. All bus transactions are terminated with the master issuing a stop
sequence.
The following timing diagram shows an example of a master commanding a HMC6352 (slave) into sleep mode by sending
the “S” command. The bottom two traces show which device is pulling the SDA line low.
START
0
1
0
0
0
0
1
0
ACK
0
1
0
1
0
0
1
1
ACK
STOP
SDA
SCL
M_SDA
S_SDA
42(hex)
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Write to This I C Address
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“S”
Command
I C bus control can be implemented with either hardware logic or in software. Typical hardware designs will release the
SDA and SCL lines as appropriate to allow the slave device to manipulate these lines. In a software implementation, care
must be taken to perform these tasks in code.
Command Protocol
The command protocol defines the content of the data (payload) bytes of I C protocol sent by the master, and the slave
device (HMC6352).
After the master device sends the 7-bit slave address, the 1-bit Read/Write, and gets the 1-bit slave device acknowledge
bit returned; the next one to three sent data bytes are defined as the input command and argument bytes. To conserve
data traffic, all response data (Reads) will be context sensitive to the last command (Write) sent. All write commands shall
have the address byte least significant bit cleared (factory default 42(hex)). These commands then follow with the ASCII
command byte and command specific binary formatted argument bytes in the general form of:
(Command ASCII Byte) (Argument Binary MS Byte) (Argument Binary LS Byte)
The slave (HMC6352) shall provide the acknowledge bits between each data byte per the I C protocol. Response byte
reads are done by sending the address byte (factory default 43(hex)) with the least significant bit set, and then clocking
back one or two response bytes, last command dependant. For example, an “A” command prompts the HMC6352 to
make a sensor measurement and to route all reads for a two byte compass heading or magnetometer data response.
Then all successive reads shall clock out two response bytes after sending the slave address byte. Table 1 shows the
HMC6352 command and response data flow.
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HMC6352
Table 1 – HMC6352 Interface Commands/Responses
Command
Byte
ASCII (hex)
w (77)
r (72)
G (47)
g (67)
S (53)
W (57)
O (4F)
C (43)
E (45)
L (4C)
A (41)
Operational Controls
HMC6352 has two parameters;
Operational Mode
and
Output Mode,
which control its operation. The Operational Mode
control byte is located at RAM register byte 74(hex) and is shadowed in EEPROM location 08(hex). This byte can be used
to control the continuous measurement rate, set/reset function, and to command the HMC6352 into the three allowed
operating modes; Standby, Query, and Continuous.
The Output Mode control byte is located at RAM register byte 4E(hex) and is not shadowed in the EEPROM, and upon
power up the device is in the Heading output mode. This byte can be changed to get magnetometer data if necessary but
is typically left in a default heading data mode.
Non-Volatile Memory
The HMC6352 contains non-volatile memory capability in the form of EEPROM that retains key operational parameters
and settings for electronic compassing. Table 2 shows the balance of the EEPROM locations that the user can read and
write to. Details on the features of these location bytes will be discussed in the following paragraphs.
Table 2 – HMC6352 EEPROM Contents
EE Address (hex)
00
01
02
03
04
05
06
07
08
Operational Modes
The HMC6352 has three operational modes plus the ability to enter/exit the non-operational (sleep) mode by command.
Sleep mode sends the internal microprocessor into clock shutdown to save power, and can be brought back by the “W”
command (wake). The “S” command returns the processor to sleep mode. The three operational modes are defined by
two bits in the internal HMC6352 Operation Mode register. If the master device sends the “L” command, the current
operational mode control byte in the RAM register is loaded into the internal EEPROM register and becomes the default
operational mode on the next power-up. The application environment of the HMC6352 will dictate the most suitable
operational mode.
Byte Description
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I C Slave Address
Magnetometer X Offset MSB
Magnetometer X Offset LSB
Magnetometer Y Offset MSB
Magnetometer Y Offset LSB
Time Delay (0 – 255 ms)
Number of Summed measurements(1-16)
Software Version Number
Operation Mode Byte
Factory Default
42(hex)
factory test value
factory test value
factory test value
factory test value
01(hex)
04(hex)
> 01(hex)
50(hex)
Argument 1 Byte
(Binary)
EEPROM Address
EEPROM Address
RAM Address
RAM Address
Argument 2
Byte
(Binary)
Data
Data
Data
Response 1
Byte
(Binary)
Data
Response 2
Byte
(Binary)
MSB Data
LSB Data
Description
Write to EEPROM
Read from EEPROM
Write to RAM Register
Read from RAM Register
Enter Sleep Mode (Sleep)
Exit Sleep Mode (Wakeup)
Update Bridge Offsets (S/R Now)
Enter User Calibration Mode
Exit User Calibration Mode
Save Op Mode to EEPROM
Get Data. Compensate and
Calculate New Heading
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