Short Form Data Sheet
April 2012
8-Input, 14-Output, Dual DPLL Timing IC
with Sub-ps Output Jitter and 1588 Clock
General Description
The DS31408 is a flexible, high-performance timing IC
for diverse frequency conversion and frequency
synthesis applications. On each of its eight input clocks
and fourteen output clocks, the device can accept or
generate nearly any frequency between 2kHz and
750MHz. The device offers two independent DPLLs to
serve two independent clock-generation paths. The
input clocks are divided down, fractionally scaled as
needed, and continuously monitored for activity and
frequency accuracy. The best input clock is selected,
manually or automatically, as the reference clock for
each of the two flexible, high-performance digital PLLs.
Each DPLL lock to the selected reference and provides
programmable bandwidth, very high resolution holdover
capability, and truly hitless switching between input
clocks. The digital PLLs are followed by a clock
synthesis subsystem that has seven fully programmable
digital frequency synthesis blocks, three high-speed
low-jitter APLLs, and 14 output clocks, each with its own
32-bit divider and phase adjustment. The APLLs
provide fractional scaling and output jitter less than 1ps
RMS. For telecom systems, the DS31408 has all
required features and functions to serve as a central
timing function or as a line card timing IC.
In addition the DS31408 has an embedded IEEE 1588
clock that can be steered by system software to follow a
time master elsewhere in the system or elsewhere in
the network. This clock has all necessary features to be
the central time clock in a 1588 ordinary clock,
boundary clock or transparent clock.
DS31408
Features
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Eight Input Clocks
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Differential or CMOS/TTL Format
Any Frequency from 2kHz to 750MHz
Fractional Scaling for 64B/66B and FEC
Scaling (e.g., 64/66, 237/255, 238/255) or Any
Other Downscaling Requirement
Continuous Input Clock Quality Monitoring
Hitless Reference Switching on Loss of Input
Automatic or Manual Phase Build-Out
Holdover on Loss of All Inputs
Programmable Bandwidth, 0.5mHz to 400Hz
Each Can Slave to Either DPLL
Produce Any 2kHz Multiple Up to 77.76MHz
Output Frequencies to 750MHz
High Resolution Fractional Scaling for FEC and
64B/66B (e.g., 255/237, 255/238, 66/64) or Any
Other Scaling Requirement
Less than 1ps RMS Output Jitter
Simultaneously Produce Three Low-Jitter Rates
from the Same Reference (e.g., 622.08MHz for
SONET, 255/237*622.08MHz for OTU2, and
156.25MHz for 10GE)
Nearly Any Frequency from < 1Hz to 750MHz
Each Group Slaves to a DFS Clock, Any APLL
Clock, or Any Input Clock (Divided and Scaled)
Each Has a Differential Output (3 CML, 4 LVDS/
LVPECL
) and
Separate CMOS/TTL Output
32-Bit Frequency Divider Per Output
Steerable by Software with 2 ns Time Resolution
and
-32
2 ns Frequency Resolution
4ns Input Timestamp Accuracy and Output Edge
Placement Accuracy
Programmable Clock and Time-Alignment I/O to
Synchronize All 1588 Devices in Large Systems
Supports 1588 OC, BC, and TC Architectures
Suitable Line Card IC or Timing Card IC for Stratum
2/3E/3/4E/4, SMC, SEC/EEC, or SSU
Accepts and Produces Nearly Any Frequency from
1Hz Up to 750MHz
Internal Compensation for Local Oscillator Frequency Error
SPI™ Processor Interface
1.8V Operation with 3.3V I/O (5V Tolerant)
-8
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Two High-Performance DPLLs
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Seven Digital Frequency Synthesizers
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Three Output APLLs
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14 Output Clocks in Seven Groups
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Applications
Frequency Conversion and IEEE1588 Time/Frequency
Applications in a Wide Variety of Equipment Types
Telecom Line Cards or Timing Cards with Any Mix of
SONET/SDH, Synchronous Ethernet and/or OTN
Ports in WAN Equipment Including MSPPs, Ethernet
Switches, Routers, DSLAMs, and Base Stations
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IEEE 1588 Clock Features
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Ordering Information
PART
DS31408GN
DS31408GN+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
256 CSBGA
256 CSBGA
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General Features
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+Denotes
a lead(Pb)-free/RoHS-compliant package.
SPI is a trademark of Motorola, Inc.
1
Short Form Data Sheet
Typical Line Card Application Example, Traditional Frequency Synchronization
clock monitoring and selection,
hitless switching, holdover, frequency
conversion, fractional scaling,
jitter attenuation
19.44MHz, 38.88MHz,
25MHz, etc.
DS31408
DS31408
system timing
from master and slave
timing cards
line timing
to master and slave
timing cards
IC1
IC2
DPLL1 Path
n
OC1 to OC5
clocks to line card SERDES
SONET/SDH, 1GE, 10GE, OTN, FC, etc.
3 unrelated frequencies simultaneously with <1ps rms jitter
plus other frequencies with somewhat higher jitter
OC6
OC7
DPLL2 Path
n
IC3 to IC8
recovered line clocks from SERDES
SONET/SDH, 1GE, 10GE, OTN, FC etc.
frequencies can be unrelated to one another
8kHz, 19.44MHz,
38.88MHz, 25MHz, etc.
clock monitoring and selection,
undo fractional scaling,
frequency conversion
155.52M, 622.08M, 25M,
125M, 156.25M, etc. with or
without fractional scaling for
FEC, 64B/66B, etc.
MANY other rates possible,
including DS1, E1, DS3, E3,
10M and Nx19.44M.
Typical Application Example, Frequency and Time Synchronization
Processor
1588
Software
Local OSC
TCXO or
OCXO
SPI
packet data to/from central switch function
DS31408
from port cards,
for SyncE or
1588+SyncE operation
line clocks, e.g. 25MHz
DPLL
1588
Clock
system time, e.g. 1 PPS
system clock, e.g. 25MHz
other clocks
to all port cards
3
Short Form Data Sheet
DS31408
Detailed Features
Input Clock Features
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Eight input clocks, differential or CMOS/TTL signal format
Input clocks can be any frequency from 2kHz up to 750MHz
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, OTU-3
Per-input fractional scaling (i.e., multiplying by N÷D where N is a 16-bit integer and D is a 32-bit integer
and N < D) to undo 64B/66B and FEC scaling (e.g., 64/66, 238/255, 237/255, 236/255)
Special mode allows locking to 1Hz input clocks
All inputs constantly monitored by programmable activity monitors and frequency monitors
Fast activity monitor can disqualify the selected reference after a few missing clock cycles
Frequency measurement and frequency monitor thresholds with 0.2ppm resolution
Three optional 2/4/8kHz frame-sync inputs
DPLL Features
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Very high-resolution DPLL architecture
Sophisticated state machine automatically transitions between free-run, locked, and holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 0.5mHz to 400Hz
Separately configurable acquisition bandwidth and locked bandwidth
Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20
Multiple phase detectors: phase/frequency and multicycle
Phase/frequency locking (±360° capture) or nearest edge phase locking (±180° capture)
Multicycle phase detection and locking (up to
±8191UI)
improves jitter tolerance and lock time
Phase build-out in response to reference switching for true hitless switching
Less than 1 ns output clock phase transient during phase build-out
Output phase adjustment up to
±200ns
in 6ps steps with respect to selected input reference
High-resolution frequency and phase measurement
Holdover frequency averaging over 1-second, 5.8-minute, and 93.2-minute intervals
Fast detection of input clock failure and transition to holdover mode
Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks
Digital Frequency Synthesizer Features
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Seven independently programmable DFS blocks
Each DFS can slave to either of the DPLLs
Each DFS can synthesize any 2kHz multiple up to 77.76MHz
Per-DFS phase adjust (1/256UI steps)
Approximately 40ps RMS output jitter
Output APLL Features
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Simultaneously produce three high-frequency, low-jitter, rates from the same reference clock, e.g.,
622.08MHz for SONET, 255/237*622.08MHz for OTU2, and156.25MHz for 10GE
Standard telecom output frequencies include 622.08MHz, 155.52MHz, and 19.44MHz for SONET/SDH
and 156.25MHz, 125MHz, and 25MHz for Synchronous Ethernet
Very high-resolution fractional scaling (i.e., noninteger multiplication)
Less than 1ps RMS output jitter
5
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