R
EM MICROELECTRONIC -
MARIN SA
EM6812
Ultra Low Power 8-bit FLASH Microcontroller
Description
The EM6812 is designed to be battery operated for extended
lifetime applications. Brownout and powercheck functions
ensure reliable operation at or near undervoltage conditions,
offering greater reliability in complex operation modes. Each
of the 16 I/Os is freely programmable and the microcontroller
has a dual quartz and trimmable RC oscillator up to 10MHz. It
has an 8-bit RISC architecture specially designed for very low
power consumption. With 2 clocks per instruction, EM6812
executes up to 2.5 MIPS at 5MHz and achieves an
astonishing 2200 MIPS/Watt.
Block Diagram
Power Supply
&
Voltage Regulator
Supply Voltage
Level Detector
8-level
Power On
Reset
Brownout
SECURITY
FLASH
22.5 kByte
11.2 kByte
5.6 kByte
CoolRISC 8-bit
CR816L
16 registers
Hardware multiplier
RAM
512x8 bit
Low Power
RAM
12x8 bit
CORE
&
MEMORY
Dual Port
RAM
4x8 bit
RC 1-10MHz
Crystal 32kHz
Prescaler 1
Prescaler 2
Watchdog
IRQ
4 x 8 bit
(2 x 16 bit)
Timer
CLOCK
&
TIMING
Features
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Green mold / leadfree package
True low current:
120 µA active mode
6 µA standby mode, RC on
0.8 µA standby mode, RC off
Up to 2.5 MIPS at 5MHz
On-chip brownout detection
Powercheck functions at start-up
8-level Supply Voltage Level Detection (SVLD)
Fast wake-up from standby mode
16 fully configurable I/Os
"
Input / Output
"
Pull-up, Pull-down
"
CMOS, N-channel open drain
6 high currents outputs, up to 20 mA
Wide supply voltage range 2 V – 5.5 V
Flash read monitor (allows save instruction execution
at lowest voltages)
Dual mode quartz and RC oscillators:
"
1 MHz – 10 MHz RC
"
32768 Hz crystal or external clock source
8-bit CoolRISC architecture
"
16 registers
"
2 clock per instruction
"
8x8bit hardware multiplier
Power-On-Reset and watchdog
Various Flash memory size:
"
2k x 22 bit (5.6k Byte)
"
4k x 22 bit (11.2k Byte)
"
8k x 22 bit (22.5k Byte)
Fully static 512B or 256B RAM, Low power 12B RAM,
Dual port 4B RAM
Internal and external interrupts
Frequency generator
PWM functions
8/16-bit timers
Prescaler:
"
10-bit RC divider
"
15-bit crystal divider
SPI interface, UART programmable by software
Small 24-pin TSSOP and SO packages (leadfree)
PORT A
Pull-up/-down, Edge, Debounce
PORT B
SPI, soft UART, PWM,
Frequency generator
I/Os
Tools & Services
!
Easy to use emulator with full debug functions, full
peripheral integration, C-compiler
!
Windows-based software programs
!
Programmer from different vendors
!
Dedicated team of engineers for outstanding support
Pinout Configuration
PB4
PB5
PB6
PB7
V
REG
V
DD
OSC OUT
OSC IN
PA7
PA6
PA5
PA4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
EM6812
TSSOP-24
SO-24
Package
(top view)
22
21
20
19
18
17
16
15
14
13
PB3
PB2
PB1
PB0
N.C.
V
SS
TEST
RESET
PA0
PA1
PA2
PA3
Typical Applications
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Metering
Heat Cost Allocation
Smoke detector
Security
Body care
Sports
Computer peripherals, Bluetooth chipset
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EM6812
1
"
"
"
EM6812 at a glance
Prescaler’s
"
"
"
"
"
2 Prescaler for RC and Xtal Oscillators
input clock software selectable
fix interval IRQ’s (RTC and others)
clock source to other peripherals
Divider capture, 8 MSB’s
Low power architecture
Voltage regulator for internal logic supply
External regulator capacitor
Power supply
CPU
"
"
"
"
"
8 bit CoolRisc 816L Core
16 internal registers
4 hardware subroutine stacks
8 bit hardware multiplier
refer also to the CR816L reference manual
Parallel In/Output Port A
"
"
"
"
"
"
"
"
"
8 bit wide direct input read
all functions bit-wise configurable
Input , output
debouncer
IRQ on pos. or neg. edge
Pull-up, pull-down or no pull selectable
Freq. Input for timer
Input combination reset
CMOS or NCH. Open Drain outputs
ROM / Flash
"
"
ROM 4096 Instructions = 11.26 Kbytes
Flash 8192 Instructions = 22.5 Kbytes
RAM
"
"
"
512 x 8 bit static SRAM (for 8k Instructions)
256 x 8 bit static SRAM (for < 4k Instructions)
low voltage ram data retention
Parallel In/Output Port B
"
"
"
"
"
"
"
"
8 multipurpose I/O’s
8 bit wide direct input read
all functions bit-wise configurable
4 high current outputs
Input , output
Pull-up, pull-down or no pull selectable
CMOS or NCH. Open Drain outputs
special function: Serial Interface I/O’s, DP RAM
Low power RAM, 12 Byte
"
for lowest power calculations
Dual Port RAM, 4 Byte
"
Data IO on port B, Control on port A
Serial Interface SPI
"
3 wire serial Interface, Sclk, Din, Dout
Operating modes
"
"
"
"
Active mode: CPU and peripherals are running
Standby mode: CPU halted, peripherals on
Sleep mode: no clocks, reset state
Wake Up from port A inputs
Timer (4 x 8 bit, or 2 x 16 bit)
"
"
"
"
"
8 (16) bit wide, Zero-Stop and Auto-Reload mode
External signal pulse width measurement
PWM generation
Event Counter
IRQ requests
Resets
"
"
"
"
"
"
Power On Reset
Reset from watchdog timer
External Reset Input
Brown Out
Reset with Port A reset combination
Reset Flags to identify the reset source
Watchdog timer
"
generation of watchdog reset after time out
Interrupt
"
"
external IRQ’s from Port A, Comparator
internal IRQ’s from Timer, Prescaler
Oscillator XTAL 32kHZ
"
"
Oscillation clock pre-divider (1 sec)
External clock low frequency input
SVLD
"
8 levels supply voltage level check
Oscillator RC
"
"
"
"
"
internal RC oscillator
External clock high frequency input
Freq. Trimming register
1MHz or 10MHz Clocks
stable over temperature and voltage
Brown Out
"
"
On-chip Brown-Out detection, reset state
Power check at Startup
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EM6812
Table of contents
1 EM6812 at a glance
2 Circuit Connectivity
2.1
2.2
Terminal usage
Programming connections
Active mode
Standby Mode
Sleep Mode
System registers
Memory miss
2
5
6
7
3
Operating modes
3.1
3.2
3.3
3.4
8
8
8
8
9
10.3.2
Input splitting
10.3.3
Actions
10.3.4
Condition match
10.3.5
Don’t care bits
10.3.6
Debouncer
10.4
Oscillation Loop
10.4.1
Inverter function
10.5
Dual Port RAM interface
40
40
40
41
41
41
41
41
11 Port B
11.1
Basic features
11.1.1
Special function priority handling
11.1.2
Overview
11.2
Register map, PB IO functions
11.3
Normal IO operation
11.4
Special IO operation
11.4.1
Frequency Output
11.4.2
SPI outputs
11.4.3
SPI inputs
11.4.4
Dual Port RAM terminals
42
42
42
43
44
45
45
45
46
46
46
4
5
Program Memory
4.1
10
10
Data Memory
5.1
SRAM
5.2
General Purpose Registers, 16 Bytes
5.3
Dual Port RAM
5.3.1
CPU R/W access to DPR
5.3.2
External Write Access to DPR
5.3.3
Read Access from DPR
5.3.4
Conflict handling
5.3.5
Register overview
12
12
13
13
13
14
14
15
15
12 Serial Port Interface
12.1
Basic features:
12.1.1
Overview:
12.1.2
SPI terminal configuration
12.2
Functionality
12.2.1
Master and Slave modes
12.2.2
Fix data stream Output (Auto-Start)
12.2.3
SPI Interruptions
12.2.4
SPI edge and synchronization selection
12.2.5
SPI start-up
12.2.6
MSB or LSB first selection
12.3
Registers overview:
47
47
47
48
48
48
48
48
49
49
49
50
6
7
CPU
Reset Controller
7.1
Basic features
7.1.1
Reset functions registers
7.2
POR and PowerCheck
7.3
Reset Pad
7.4
PortA Input Reset
7.5
BrownOut reset
7.5.1
BO Timings
7.6
Watchdog
7.6.1
Watchdog counter
7.6.2
Lock/Unlock
16
17
17
18
19
20
20
21
21
22
22
22
13 Timers
13.1
Basic features:
13.2
Functionality
13.2.1
Auto-Reload mode
13.2.2
Zero-Stop mode
13.2.3
Start control system
13.2.4
Stopping the timer
13.2.5
Clock selection
13.2.6
PWM and Frequency generation
13.2.7
16-bits configuration
13.2.8
Interrupts
13.3
Recommended programming order
13.4
Registers overview:
13.4.1
General configuration registers
13.4.2
Timer1 configuration
13.4.3
Timer2 configuration
13.4.4
Timer3 configuration
13.4.5
Timer4 configuration
51
51
52
52
53
54
57
57
57
58
59
60
60
60
61
62
63
64
8
Clock management
8.1
Basic features
8.1.1
Overview
8.2
High frequency clock source
8.2.1
RC oscillator
8.2.2
High frequency external clock
8.3
Low frequency clock source:
8.3.1
Crystal oscillator
8.3.2
Low frequency external clock
8.3.3
Data input on OscOut
8.4
Clock synchronization
8.5
CPU clock selection
8.6
Peripheral clocks generation
8.6.1
Prescaler2 (10 stages)
8.6.2
Prescaler1 (15 stages)
8.7
RC clock trimming with Xtal oscillator
8.8
Registers overview
23
23
23
24
24
25
26
26
27
27
27
28
28
29
30
31
32
14 Interruptions
14.1
Basic features
14.2
Interrupt acquisition
14.2.1
Interrupt acquisition masking.
14.2.2
Interrupt acquisition Clearing
14.2.3
Register map, Interrupt acquisition
14.3
CPU Interrupt and Event handling
14.3.1
Interrupt priority
14.3.2
CPU Status register
14.3.3
CPU Status register pipeline exception
14.3.4
Processor vector table
14.3.5
Context Saving
65
65
66
67
67
67
68
68
69
69
70
70
9 Supply Voltage Level Detector (SVLD)
10 Port A
10.1
Basic features
10.1.1
Overview
10.1.2
Register map, PA IO functions
10.1.3
IO Operation
10.2
Port A Interrupt requests
10.2.1
Debouncer
10.3
Reset and Wake-up
10.3.1
Register map
Copyright
©
2004, EM Microelectronic-Marin SA
33
34
34
35
36
37
38
38
39
40
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EM6812
Memory mapping
16 Typical V and T dependencies
16.1
16.2
16.3
16.4
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
IVDD Currents
SVLD, BO Detection levels
IOL and IOH drives
Pullup and Pulldown
71
74
74
75
75
75
17 Electrical Specification
76
Absolute Maximum Ratings
76
Handling Procedures
76
Standard Operating Conditions
76
Typical Crystal specification
76
DC Characteristics - Power Supply Currents 76
DC Characteristics – Voltage detection levels77
DC Characteristics – Oscillators
77
DC Characteristics - I/O Pins
78
Package drawings
79
18 Ordering information Flash device
80
19 Datasheet History
Error! Bookmark not defined.
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©
2004, EM Microelectronic-Marin SA
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EM6812
2
Circuit Connectivity
The EM6812 has the same pin-out in both the SO24 and TSSOP24 pin package.
Minimum connectivity includes the power supply on V
SS
and V
DD
, a capacitor on on Vreg, and de-coupling capacitance on
V
DD
. Circuit reference terminal (substrate) is on V
SS
.
The 32kHz XTAL is only needed for systems requiring low frequency Crystal operation.
The integrated supply voltage regulator filters supply noise and allows lowest power peripheral operations. For proper
operation, a capacitor (470nF minimum) must be connected to the regulator’s VREG terminal. This terminal must not be
used for any other outside connection.
Figure 1: Sample minimum connectivity
24
PB4
PB5
PB6
PB7
Vreg
VDD
PB3
PB2
PB1
PB0
i.c.
VSS
10k
Test
Reset
Reset
PA0
PA1
PA2
PA3
Button
VDD
VSS
1
2
3
4
23
22
21
EM6812
20
5
6
19
VDD
OscOut
32khz
OscIn
Shield
with
VSS
PA7
PA6
PA5
PA4
470nF
18
7
VSS
17
Note:
•
ALL circuit IO's (except OscIn) are on V
DD
level. OscIn terminal is only used in conjunction with an active Crystal
oscillator. Its input voltage must never exceed the Vreg voltage.
•
The crystal oscillator should be shielded with V
SS
to keep noise away.
•
When using the Crystal oscillator PA[7] and PA[6] should preferably used as static inputs only to avoid noise coupling
on the OscIn and OscOut high impedance inputs.
8
9
10
11
12
16
15
14
13
Copyright
©
2004, EM Microelectronic-Marin SA
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