Functionally compatible with traditional asynchronous
SRAMs
Equal address and chip-enable access times
HiRel temperature range (-40
o
C to 105
o
C)
Automatic data protection with low-voltage inhibit
circuitry to prevent writes on power loss
CMOS and TTL compatible
Data retention: 20 years (-40
o
C to 105
o
C)
Read/write endurance: unlimited for 20 years (-40
o
C to
105
o
C)
Operational environment:
- Total dose: 1Mrad(Si)
- SEL Immune: 112 MeV-cm
2
/mg @125
o
C
- SEU Immune: Memory Cell 112 MeV-cm
2
/mg @25
o
C
Two 40-pin package options available
Standard Microelectronics Drawing 5962-12227
- QML Q, Q+
- QML V pending
INTRODUCTION
The Aeroflex 16Megabit Non-Volatile magnetoresistive
random access memory (MRAM) is a high-performance
memory compatible with traditional asynchronous SRAM
operations, organized as a 2,097,152 words by 8bits.
The MRAM is equipped with chip enable (/E), write enable
(/W), and output enable (/G) pins, allowing for significant
system design flexibility without bus contention. Data is non-
volatile for > 20 year retention at temperature and data is
automatically protected against power loss by a low voltage
write inhibit.
The 16Mb MRAM is designed specifically for operation in
HiRel environments. As shown in Table 3, the magneto-resistive
bit cells are immune to Single Event Effects (SEE). To guard
against transient effects, an Error Correction Code (ECC) is
included within the device. ECC check bits are generated and
stored within the MRAM array during writes. If a single bit error
is found during a read cycle, it is automatically corrected in the
data presented to the user.
Figure 1. UT8MR2M8 MRAM Block Diagram
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Aeroflex Microelectronic Solutions - HiRel
PIN NAMES
Table 1. 2M x 8 Pin Functions
ZZ/RST
A0
A1
A2
A3
A4
/E
DQ0
DQ1
VDD
VSS
DQ2
DQ3
/W
A5
A6
A7
A8
A9
NUIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NUIO
A20
A19
A18
A17
A16
/G
DQ7
DQ6
VSS
VDD
DQ5
DQ4
A15
A14
A13
A12
A11
A10
VSS
Signal Name
A[20:0]
/E
/W
/G
DQ[7:0]
VDD
VSS
ZZ/RST
NUIO
Function
Address Input
Chip Enable
Write Enable
Output Enable
Data I/O
Power Supply
Ground
Deep Power Down/
Reset
Not used input/output
Recommend tie low
Figure 2. Package (X) 40-lead CFP-50 Mil Pitch
DEVICE OPERATION
A16
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
A19
NUIO
VSS
A18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A15
ZZ/RST
NUIO
/W
A20
A13
A8
A9
A11
/G
A10
/E
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
A17
The UT8MR2M8 has four control inputs called Chip Enable
(/E), Write Enable (/W), Output Enable (/G) and Sleep/Reset
Mode (ZZ/RST); 21 address inputs, A[20:0]; and eight
bidirectional data lines, DQ[7:0]. /E controls device selection,
active, and standby modes. Asserting /E enables the device,
causes I
DD
to rise to its active value, and decodes the 21 address
inputs to select one of 2,097,152 words in the memory. /W
controls read and write operations. During a read cycle, /G must
be asserted to enable the outputs. ZZ/RST controls the sleep/
reset mode operation and provides device reset capability.
Enabling sleep/reset mode causes all other inputs to be don’t
cares. The following descriptions assume that sleep/reset mode
is disabled when ZZ/RST is logic low.
Table 2. Device Operation Truth Table
ZZ/
Reset
H
L
L
L
L
/E
X
H
L
L
L
/G
X
X
H
L
X
/W
X
X
H
H
L
Mode
Deep Sleep/
Reset Mode
Not Selected
Output
Disabled
Byte Read
Byte Write
VDD
DQ[7:0]
Current
Q
IZZ
Q
IDD
I
DDR
I
DDR
I
DDW
HI-Z
HI-Z
HI-Z
D
OUT
D
IN
Figure 3. Package (Y) 40-lead CFP-25 Mil Pitch
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Aeroflex Microelectronic Solutions - HiRel
READ CYCLE
A combination of /W greater than V
IH
(min) and /E less than
V
IL
(max) defines a read cycle. Read access time is measured
from the latter of chip enable, output enable, or valid address
to valid data output.
MRAM Read Cycle 1, the Address Access in Figure 5a, is
initiated by a change in address inputs while the chip is enabled
with /G asserted and /W deasserted. Valid data appears on data
outputs DQ[7:0] after the specified t
AVQV
is satisfied. Outputs
remain active throughout the entire cycle. As long as chip
enable and output enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (t
AVAV
).
MRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 5b, is initiated by /E going active while /G remains
asserted, /W remains deasserted, and the addresses remain
stable for the entire cycle. After the specified t
ELQV
is satisfied,
the eight-bit word addressed by A[20:0] is accessed and
appears at the data outputs DQ[7:0].
WRITE CYCLE
A combination of /W and /E less than V
IL
(max) defines a write
cycle. The state of /G is a “don’t care” for a write cycle. The
outputs are placed in the high-impedance state when either /G
is greater than V
IH
(min), or when /W is less than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access in Figure
6a, is defined by a write terminated by /W going high, with /E
still active. The write pulse width is defined by t
WLWH
when
the write is initiated by /W, and by t
WLEH
when the write is
initiated by /E. Unless the outputs have been previously placed
in the high-impedance state by /G, the user must wait t
WLQZ
before applying data to the eight bidirectional pins DQ[7:0] to
avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access in Figure
6b, is defined by a write terminated by /E going inactive. The
write pulse width is defined by t
ELWH
when the write is initiated
by /W, and by t
ELEH
when the write is initiated by /E going
active. For the /E initiated write, unless the outputs have been
previously placed in the high-impedance state by /G, the user
must wait t
WLQZ
before applying data to the eight bidirectional
pins DQ[7:0] to avoid bus contention.
OPERATIONAL ENVIRONMENT
The UT8MR2M8 MRAM incorporates special design and
layout features which allows operation in harsh environments.
Table 3. Operational Environment
Design Specifications
PARAMETER
TID
SEL Immunity
1
SEU Memory Cell
Immunity
2
Notes:
1. SEL test performance at V
DD
= 3.6V and temperature= 125
o
C.
2. SEU test performance at V
DD
= 3.0V and unpowered at room temperature.
LIMIT
1
< 112
< 112
UNITS
Mrad(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
POWER UP AND POWER DOWN SEQUENCING
The MRAM is protected from write operations whenever
V
DD
is less than V
WI
. As soon as V
DD
exceeds V
DD
(min),
there is a startup time of 2 ms before read or write operations
can start. This time allows memory power supplies to
stabilize. The /E and /W control signals should track V
DD
on
power up to V
DD
- 0.2 V or V
IH
(whichever is lower) and
remain high for the startup time. In most systems, this means
that these signals should be pulled up with a resistor so the
signal remains high if the driving signal is Hi-Z during power
up. Any logic that drives /E and /W should hold the signals
high with a power-on reset signal for longer than the startup
time. During power loss or brownout where V
DD
goes below
V
WI
, writes are protected and a startup time must be observed
when power returns above V
DD
(min).
The MRAM supports sleep/reset mode operation using the
ZZ/RST control pin. To enter sleep/reset mode, ZZ/RST must
be pulled high. The device will enter sleep/reset mode within
40ns. In order to exit sleep/reset mode, /E and /W must be
high before ZZ/RST is pulled low. As soon as ZZ/RST is
driven low, the user must allow 100us before performing any
other operation in order for the device to properly initialize.
Aeroflex recommends designing a system level method to
toggle the ZZ/RST pin in order to reset the MRAM device.
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Aeroflex Microelectronic Solutions - HiRel
Figure 4. UT8MR2M8 Power Up and Power Down Sequencing Diagram
36-00-01-002
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Aeroflex Microelectronic Solutions - HiRel
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
The device contains protection against magnetic fields. Precautions should be taken to avoid device exposure of any magnetic field
intensity greater than specified.
SYMBOL
V
DD
V
IN
I
IO
P
D
T
J
θ
JC
T
STG
ESD
HBM
H
max_write
H
max_read
Supply Voltage
2
Voltage on any pin
2
DC I/O current per pin @ T
J
= 125° for 20yrs
Package power dissipation permitted
3
Maximum junction temperature
Thermal resistance junction to case
Storage temperature
ESD (Class 2)
Maximum magnetic field during write
Maximum magnetic field during read or standby
PARAMETER
VALUE
-0.5 to 4.3
-0.5 to V
DD
+0.5
±
20
4
+125
5
-65 to +125
2000
8000
8000
o
UNIT
V
V
mA
W
o
C
C/W
o
C
V
A/m
A/m
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions.
Exposure to excessive voltages or magnetic fields could affect device reliability.
2. All voltages are referenced to V
SS
.
3. Power dissipation capability depends on package characteristics and use environment.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
T
C
V
DD
V
WI
V
IH
V
IL
PARAMETER
Operating case temperature
Operating supply voltage
Write inhibit voltage
Input high voltage
Input low voltage
LIMITS
-40 to +105
o
C
3.0V to 3.6V
2.5V to 3.0V
1
2.0V to V
DD
+0.3V
V
SS
-0.3V to 0.8V
Notes:
1. After power up or if V
DD
falls below V
WI
, a waiting period of 2 ms must be observed, and /E and /W must remain high for 2 ms. Memory is designed to prevent
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