208-MHz, 32-bit
microcontroller with
ARM9EJ-S
™
core
LPC3180
Low-power, ARM9-based
microcontroller
A USB OTG interface with full host capability lets this high-performance microcontroller connect
directly to peripherals. Other options – including seven UARTs, two SPI, two I
2
C, a real-time clock
with separate power domain, and controllers for NAND Flash and SDRAM memory – increase
design flexibility.
Key features
4
08-MHz, 32-bit ARM9EJ-S with AHB/APB interfaces
2
4
0-nm technology for operation down to 0.9 V in low-
9
power mode
4
ector floating-point coprocessor
V
4
xternal memory interface for Flash, SDR, and DDR
E
SDRAM
4
5 KB of SRAM, 32 K of instruction and data cache
6
4
SB OTG with full-speed host capability
U
4
eneral-purpose DMA controller and memory
G
management unit
4
0-bit A/D converter
1
4
ultiple serial interfaces: two I
2
C, two SPI, seven UART
M
4
wo 32-bit timers and real-time clock with separate clock
T
and power domain
4
TAG interface with emulation-trace buffer
J
4
.2-V core voltage, 3-V and 1.8-V I/O
1
4
ecure Digital (SD) memory-card interface
S
4
ackage: LFBGA320 (13 x 13 x 0.9 mm)
P
Applications
4
ndustrial
I
4
edical
M
4
eripheral control: printers, scanners, POS
P
4
edical devices
M
4
PS, motors, security devices, servo loops
G
4
etwork control
N
The NXP microcontroller LPC3180, a 32-bit microcontroller
built around a 90-nm ARM9 core, is the industry’s first to pro-
vide a vector floating-point co-processor, integrated USB On-
The-Go (OTG), and the ability to operate in ultra-low-power
mode (down to 0.9 V).
The ARM9 core operates at up to 208 MHz and is supported
by 32 K of data cache and 32 K of instruction cache. There is
an external-memory interface for NAND Flash and SDRAM
memory (at 1.8 V for mobile SDRAM), and a 64-KB block of
on-chip SRAM.
The on-chip memory management unit (MMU) supports major
operating systems, including Linux, the leading OS for embed-
ded applications. Also, the on-chip Java byte-code coproces-
sor supports basic security and authentication applications.
The vector floating-point coprocessor increases the speed of
typical calculations by a factor of four to five in scalar mode,
and much more in optimized vector mode.
Flexible power management enables high peak performance,
especially for floating-point calculations, and can be used to
shut down the core power domain while retaining real-time-
clock and wake-up functionality.
Multiple serial communications interfaces increase design flex-
ibility, provide larger buffer size, and deliver higher processing
power. The USB 2.0 device supports On-The-Go (OTG) and
has full speed host capabilities. There are seven 16C550 UARTs
(one supports IrDA), two Fast I
2
C-bus (400 Mbps) interfaces,
two SPI interfaces, and an automatic keyscan function that sup-
ports 8 x 8 keys.
There is a 10-bit A/D converter with three channels, two 32-bit
timers with four capture/compare channels, two PWM chan-
nels, a PLL, a real-time clock with separate clock and power
domain, a Watchdog timer, and a Secure Digital (SD) memory-
card interface. The core voltage supports 1.2 V, while the I/O
ports support 1.8 and 3.0 V. The operating temperature range
is -40 to 85 °C.
For debugging, the LPC3180 supports real-time emulation,
has an on-chip embedded-trace buffer with a 2K x 24-bit RAM,
and an integrated interrupt controller. Also, for compatibility
with existing tools, it uses the standard ARM test/debug JTAG
interface.
Third-Party Development Tools
Through third-party suppliers, we offer a range of develop-
ment tools for our microcontrollers. For the most current list-
ing, please visit www.nxp.com/microcontrollers.
External Memory I/F
(NAND, SD, and DRAM)
E-ICE/RTM Interface
Embedded Trace Buffer
64-KB SRAM
Interrupt Controller
DMA
Vector Floating–Point Coprocessor
MMU
32-bit ARM926EJ-S
Bus Matrix
32-K D Cache
32-K I Cache
Power Management, Real-time Clock,
Watchdog Timer, PLL
10-bit A/D Converter
(Three Channels)
Two timers with
Capture / Compare
2 x I
2
C
(Master Only)
UART 1-7
(UART6 supports IrDA)
USB 2.0
Full-speed / Host / OTG
2 x PWM
(1 Channel Each)
2 x SPI
(Master Only)
Keyscan
I/O ports (55)
LPC3180 block diagram
LPC3180 selection guide
Type
LPC3180
(1)
External memory
interface
1
SRAM
64 KB
I-cache
32 K
D-cache
32 K
USB 2.0
(12 or 480 Mbps) + OTG
1
I
2
C
2
SPI
2
UARTs
6
(1)
ADC channels
(10-bit)
3
Package
LFBGA320
UART6 supports IrDA
www.nxp.com
© 2006 NXP N.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and
may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof
does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Date of release: October 2006
Document order number: 9397 750 15694
Printed in the USA
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