MT41K1G4RH-125M:E datasheet, PDF

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MT41K1G4RH-125M:E: DescriptionDDR DRAM, 1GX4, CMOS, PBGA78, FBGA-78; Categorystorage storage; File Size580KB，29 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT41K1G4RH-125M:E Overview

DDR DRAM, 1GX4, CMOS, PBGA78, FBGA-78

MT41K1G4RH-125M:E Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	1250477723
package instruction	TFBGA,
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B78
length	10.5 mm
memory density	4294967296 bit
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	78
word count	1073741824 words
character code	1000000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	1GX4
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.45 V
Minimum supply voltage (Vsup)	1.283 V
Nominal supply voltage (Vsup)	1.35 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	9 mm

MT41K1G4RH-125M:E Preview

4Gb: x4, x8, x16 DDR3L-RS SDRAM

Description

1.35V DDR3L-RS SDRAM

MT41K1G4 - 128 Meg x 4 x 8 banks

MT41K512M8 – 64 Meg x 8 x 8 banks

MT41K256M16 – 32 Meg x 16 x 8 banks

Description

The 1.35V DDR3L-RS SDRAM device is a low-current

self refresh version of the 1.35V DDR3L SDRAM device

via the TCSR feature. Unless stated otherwise, the

DDR3L-RS SDRAM device meets the functional and

timing specifications listed in the equivalent density

standard or automotive DDR3L SDRAM data sheet lo-

cated on www.micron.com.

Features

• Self refresh temperature (SRT)

• Automatic self refresh (ASR)

• Temperature-compensated self refresh (TCSR)

mode

• Very low current self refresh mode when room tem-

perature

Options

• Configuration

– 1 Gig x 4

– 512 Meg x 8

– 256 Meg x 16

• FBGA package (Pb-free) – x4, x8

– 78-ball (10.5mm x 12mm) Rev. D

– 78-ball (9mm x 10.5mm) Rev. E

• FBGA package (Pb-free) – x16

– 96-ball FBGA (10mm x 14mm) Rev. D

– 96-ball FBGA (9mm x 14mm) Rev. E

• Timing – cycle time

– 1.071ns @ CL = 13 (DDR3-1866)

– 1.25ns @ CL = 11 (DDR3-1600)

– 1.5ns @ CL = 9 (DDR3-1333)

– 1.875ns @ CL = 7 (DDR3-1066)

• Temperature

– Commercial (0°C

≤

+95°C)

• Power Saving

– TCSR

• Revision

Marking

1G4

512M8

256M16

-107

-125

-15E

-187E

None

:D/:E

Features

•

= V

DDQ

= 1.35V (1.283–1.45V)

Backward-compatible to V

= V

DDQ

= 1.5V ±0.075V

Differential bidirectional data strobe

8n-bit prefetch architecture

Differential clock inputs (CK, CK#)

8 internal banks

Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

Programmable CAS (READ) latency (CL)

Programmable posted CAS additive latency (AL)

Programmable CAS (WRITE) latency (CWL)

Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

Selectable BC4 or BL8 on-the-fly (OTF)

Write leveling

Output driver calibration

Multipurpose register

of 0°C to +95°C

– 64ms, 8192-cycle refresh at 0°C to +85°C

– 32ms at +85°C to +95°C

Table 1: Key Timing Parameters

Speed Grade

-107

1, 2, 3

-125

1, 2

-15E

-187E

Notes:

Data Rate (MT/s)

1866

1600

1333

1066

Target

RCD-

RP-CL

13-13-13

11-11-11

9-9-9

7-7-7

RCD

(ns)

CL (ns)

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

13.91

13.75

13.5

13.1

1. Backward compatible to 1066, CL = 7 (-187E).

2. Backward compatible to 1333, CL = 9 (-15E).

3. Backward compatible to 1600, CL =11 (-125).

PDF: 09005aef8488935b

4Gb_1_35V_DDR3L-RS.pdf - Rev. I 4/13 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x4, x8, x16 DDR3L-RS SDRAM

Description

Table 2: Addressing

Parameter

Configuration

Refresh count

Row address

Bank address

Column address

Page size

1 Gig x 4

128 Meg x 4 x 8 banks

64K (A[15:0])

8 (BA[2:0])

2K (A[11, 9:0])

1KB

512 Meg x 8

64 Meg x 8 x 8 banks

64K (A[15:0])

8 (BA[2:0])

1K (A[9:0])

1KB

256 Meg x 16

32 Meg x 16 x 8 banks

32K (A[14:0])

8 (BA[2:0])

1K (A[9:0])

2KB

Figure 1: DDR3L-RS Part Numbers

Example Part Number: MT41K512M8RH-125M:E

MT41K

Configuration

Package

Speed

PS Revision

Configuration

1 Gig x 4

512 Meg x 8

1G4

512M8

{

:D/:E

Power Saving

TCSR

Temperature

-107

-125

-15E

-187E

Note:

Revision

256 Meg x 16 256M16

Package

78-ball 10.5mm x 12mm FBGA

78-ball 9mm x 10.5mm FBGA

96-ball 10mm x 14mm FBGA

96-ball 9mm x 14mm FBGA

Commercial

None

Speed Grade

tCK = 1.071ns, CL = 13

tCK = 1.25ns, CL = 11

tCK = 1.5ns, CL = 9

tCK = 1.87ns, CL = 7

1. Not all options listed can be combined to define an offered product. Use the part catalog search on

http://www.micron.com

for available offerings.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the

part number. Micron’s FBGA part marking decoder is available at

www.micron.com/decoder.

PDF: 09005aef8488935b

4Gb_1_35V_DDR3L-RS.pdf - Rev. I 4/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x4, x8, x16 DDR3L-RS SDRAM

Ball Assignments and Descriptions

Figure 2: 78-Ball FBGA – x4, x8 (Top View)

SSQ

DQ2

SSQ

DQ3

DDQ

SSQ

DDQ

NF, NF/TDQS#

DQ0

DM, DM/TDQS

DDQ

DQS

DQ1

SSQ

NF, DQ6 DQS#

REFDQ

DDQ

NF, DQ4

CS#

RAS#

NF, DQ7 NF, DQ5

ODT

CAS#

CK#

CKE

WE#

A10/AP

BA0

BA2

A15

REFCA

BA1

A12/BC#

A11

RESET#

A13

A14

Notes:

1. Ball descriptions listed in Table 3 (page 5) are listed as “x4, x8” if unique; otherwise,

x4 and x8 are the same.

2. A comma separates the configuration; a slash defines a selectable function.

Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies

to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de-

fined in Table 3).

PDF: 09005aef8488935b

4Gb_1_35V_DDR3L-RS.pdf - Rev. I 4/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x4, x8, x16 DDR3L-RS SDRAM

Ball Assignments and Descriptions

Figure 3: 96-Ball FBGA – x16 (Top View)

DDQ

SSQ

DDQ

DQ13

DQ11

DQ15

DQ9

DQ12

DDQ

DQ14

SSQ

DDQ

SSQ

DDQ

UDQS#

UDQS

DQ10

SSQ

DDQ

SSQ

DQ2

UDM

DQ8

SSQ

DQ3

DQ0

LDM

DDQ

LDQS

DQ1

SSQ

DQ6

LDQS#

DQ7

DQ5

REFDQ

DDQ

CS#

DQ4

RAS#

ODT

CAS#

CK#

CKE

WE#

A10/AP

BA0

BA2

REFCA

BA1

A12/BC#

A11

RESET#

A13

A14

Note:

1. A slash defines a selectable function.

PDF: 09005aef8488935b

4Gb_1_35V_DDR3L-RS.pdf - Rev. I 4/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x4, x8, x16 DDR3L-RS SDRAM

Ball Assignments and Descriptions

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions

Symbol

[15:13], A12/BC#,

A11, A10/AP, A[9:0]

Type

Input

Description

Address inputs:

Provide the row address for ACTIVATE commands, and the column

address and auto precharge bit (A10) for READ/WRITE commands, to select one

location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank

(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also

provide the op-code during a LOAD MODE command. Address inputs are referenced

to V

REFCA

. A12/BC#: When enabled in the mode register (MR), A12 is sampled during

READ and WRITE commands to determine whether burst chop (on-the-fly) will be

performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table - Command in

the DDR3 SDRAM data sheet.

Bank address inputs:

BA[2:0] define the bank to which an ACTIVATE, READ,

WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode

BA[2:0] are referenced to V

REFCA

Clock:

CK and CK# are differential clock inputs. All control and address input signals

are sampled on the crossing of the positive edge of CK and the negative edge of

CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

Clock enable:

CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/

disabled is dependent upon the DDR3 SDRAM configuration and operating mode.

Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations

(all banks idle), or active power-down (row active in any bank). CKE is synchronous

for power-down entry and exit and for self refresh entry. CKE is asynchronous for

self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are

disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disa-

bled during SELF REFRESH. CKE is referenced to V

REFCA

Chip select:

CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external rank selection on systems with multiple ranks. CS# is considered

part of the command code. CS# is referenced to V

REFCA

Input data mask:

DM is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with the input data during a write access.

Although the DM ball is input-only, the DM loading is designed to match that of the

DQ and DQS balls. DM is referenced to V

REFDQ

. DM has an optional use as TDQS on

the x8.

On-die termination:

ODT enables (registered HIGH) and disables (registered LOW)

termination resistance internal to the DDR3 SDRAM. When enabled in normal

operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,

and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is

ignored if disabled via the LOAD MODE command. ODT is referenced to

REFCA

Command inputs:

RAS#, CAS#, and WE# (along with CS#) define the command

being entered and are referenced to V

REFCA

Reset:

RESET# is an active LOW CMOS input referenced to V

. The RESET# input re-

ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH

≥

0.8 × V

and

DC LOW

≤

0.2 × V

DDQ

. RESET# assertion and desertion are asynchronous.

BA[2:0]

Input

CK, CK#

Input

CKE

Input

CS#

Input

ODT

Input

RAS#, CAS#, WE#

RESET#

Input

PDF: 09005aef8488935b

4Gb_1_35V_DDR3L-RS.pdf - Rev. I 4/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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