PIC16C924 datasheet, PDF - EEWORLD Datasheet

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PIC16C924: Description8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PQFP64; Categorysemiconductor The embedded processor and controller; File Size156KB，10 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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PIC16C924 Overview

8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PQFP64

PIC16C924 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	6 V
Minimum supply/operating voltage	2.5 V
Rated supply voltage	5 V
External data bus width	0.0
Number of input and output buses	50
Line speed	4 MHz
Processing package description	10 X 10 MM, 1 MM HEIGHT, PLASTIC, TQFP-64
Lead-free	Yes
EU RoHS regulations	Yes
China RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
terminal coating	MATTE TIN
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
ADC channel	Yes
Address bus width	0.0
Number of digits	8
Maximum FCLK clock frequency	4 MHz
Microprocessor type	RISC MICROCONTROLLER
PWM channel	Yes
ROM programming	OTPROM

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PIC16C924

TABLE 1:

COMPARE OUTPUT LOW

SWITCHING

I/O Pin

State

1000

1001

101x

11xx

Change CCP to

CCPxM<3:0> =

1001

0xxx

—

1000

—

PIC16C924 Rev. A Silicon/Data Sheet Errata

The PIC16C924 (Rev. A) parts you have received con-

form functionally to the Device Data Sheet

(DS30444E), except for the anomalies described

below.

All the problems listed here will be addressed in future

revisions of the PIC16C924 silicon.

CCP Mode

CCPxM<3:0> =

1. Module: 8-bit A/D Module

If the analog port is configured so that all analog

pins are digital inputs (PCFG2:PCFG0 =

11x),

then doing a conversion on any pin of the analog

port will give a result of ADRES = 0xFF.

Work around

Configure the PCFG2:PCFG0 bits to a value that

has any pin of the analog port configured as an

analog input (such as PCFG2:PCFG0 =

100).

Conversion on any pin of the analog port (analog

or digital) will now convert as expected.

2. Module: CCP (Compare Mode)

The Compare mode may not operate as expected

when configuring the compare match to drive the

I/O pin low (CCPxM<3:0> =

1001).

When the CCP module is changed to compare

output low (CCPxM<3:0> =

1001)

from any other

non-compare CCP mode, the I/O pin will immedi-

ately be driven low, regardless of the state of the

I/O data latch. The pin will remain low when the

compare match occurs (see Table 1).

However, when the CCP module is changed to

compare output high (CCPxM<3:0> =

1000)

from

any other CCP mode, the I/O pin will immediately

be driven low, regardless of the state of the I/O

data latch. The pin will be driven high when the

compare match occurs.

Work around

To have the I/O pin high until the compare match

low occurs, force a compare match high to get the

I/O pin into the high state, then reconfigure the

compare match to force the I/O low when the com-

pare condition occurs.

3. Module: CCP (Compare Mode)

The special event trigger of the Compare mode

may not occur if both of the following conditions

exist:

• An instruction one cycle (T

) prior to a

Timer1/Compare register match has literal

data equal to the address of a CCP register

being used. Specific cases include:

Unit

CCP1

CCPR1L

CCPR1H

CCP1CON

Literal Data

15h

16h

17h

• An instruction in the same cycle as a Timer1/

Compare register match has an MSb of ‘0’.

The interrupt for the compare event will still be

generated, but no special event trigger will occur.

Work around

Use the Interrupt Service Routine instead of using

the special event trigger to reset Timer1 (and start

an A/D conversion, if applicable).



2001 Microchip Technology Inc.

DS80111B-page 1

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