K9F5608Q0B
K9F5608U0B
K9F5616Q0B
K9F5616U0B
FLASH MEMORY
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
0.0
0.1
Initial issue.
At Read2 operation in X16 device
: A
3
~ A
7
are Don’ care ==> A
3
~ A
7
are "L"
t
1. I
OL
(R/B) of 1.8V device is changed.
-min. Value: 7mA -->3mA
-typ. Value: 8mA -->4mA
2. AC parameter is changed.
tRP(min.) : 30ns --> 25ns
3. WP pin provides hardware protection and is recommended to be kept
at V
IL
during power-up and power-down and recovery time of minimum
1µs is required before internal circuit gets ready for any command
sequences as shown in Figure 15.
---> WP pin provides hardware protection and is recommended to be
kept at V
IL
during power-up and power-down and recovery time of
minimum 10µs is required before internal circuit gets ready for any
command sequences as shown in Figure 15.
0.3
1. X16 TSOP1 pin is changed.
: #36 pin is changed from Vcc
Q
to N.C .
1. In X16 device, bad block information location is changed from 256th
byte to 256th and 261th byte.
2. tAR1, tAR2 are merged to tAR.(page 12)
(before revision) min. tAR1 = 20ns , min. tAR2 = 50ns
(after revision) min. tAR = 10ns
3. min. tCLR is changed from 50ns to 10ns.(page12)
4. min. tREA is changed from 35ns to 30ns.(page12)
5. min. tWC is changed from 50ns to 45ns.(page12)
6. Unique ID for Copyright Protection is available
-The device includes one block sized OTP(One Time Programmable),
which can be used to increase system security or to provide
identification capabilities. Detailed information can be obtained by
contact with Samsung.
7. tRHZ is divide into tRHZ and tOH.(page 12)
- tRHZ : RE High to Output Hi-Z
- tOH : RE High to Output Hold
8. tCHZ is divide into tCHZ and tOH.(page 12)
- tCHZ : CE High to Output Hi-Z
- tOH : CE High to Output Hold
Draft Date
May. 15th 2001
Sep. 20th 2001
Remark
Advance
0.2
Nov. 5th 2001
Feb. 15th 2002
0.4
Apr. 15th 2002
Note : For more detailed features and specifications including FAQ, please refer to Samsung’ Flash web site.
s
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
K9F5608Q0B
K9F5608U0B
K9F5616Q0B
K9F5616U0B
FLASH MEMORY
Document Title
32M x 8 Bit , 16M x 16 Bit NAND Flash Memory
Revision History
Revision No. History
0.5
1. Add the Rp vs tr ,tf & Rp vs ibusy graph for 1.8V device (Page 33)
2. Add the data protection Vcc guidence for 1.8V device - below about
1.1V. (Page 34)
The min. Vcc value 1.8V devices is changed.
K9F56XXQ0B : Vcc 1.65V~1.95V --> 1.70V~1.95V
Pb-free Package is added.
K9F5608U0B-FCB0,FIB0
K9F5608Q0B-HCB0,HIB0
K9F5616U0B-HCB0,HIB0
K9F5616U0B-PCB0,PIB0
K9F5616Q0B-HCB0,HIB0
K9F5608U0B-HCB0,HIB0
K9F5608U0B-PCB0,PIB0
New definition of the number of invalid blocks is added.
(Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb
memory space.)
1. Pin assignment of TBGA A3 ball is changed.
(before) N.C --> (after) Vss
2.
Note is added.
(VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for
durations of 20 ns or less.)
1. Add the Protrusion/Burr value in WSOP1 PKG Diagram.
1. PKG(TSOP1, WSOP1) Dimension Change
Draft Date
Nov. 22.2002
Remark
0.6
Mar. 6.2003
0.7
Mar. 13rd 2003
0.8
Apr. 4th 2003
0.9
May. 24th 2003
1.0
1.1
Apr. 24th 2004
May. 24th 2004
Note : For more detailed features and specifications including FAQ, please refer to Samsung’ Flash web site.
s
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
2
K9F5608Q0B
K9F5608U0B
K9F5616Q0B
K9F5616U0B
FLASH MEMORY
32M x 8 Bit / 16M x 16 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F5608Q0B-D,H
K9F5616Q0B-D,H
K9F5608U0B-Y,P
K9F5608U0B-D,H
K9F5608U0B-V,F
K9F5616U0B-Y,P
K9F5616U0B-D,H
2.7 ~ 3.6V
X16
X8
Vcc Range
1.70 ~ 1.95V
Organization
X8
X16
TSOP1
TBGA
WSOP1
TSOP1
TBGA
PKG Type
TBGA
FEATURES
•
Voltage Supply
- 1.8V device(K9F56XXQ0B) : 1.70~1.95V
- 3.3V device(K9F56XXU0B) : 2.7 ~ 3.6 V
•
Organization
- Memory Cell Array
- X8 device(K9F5608X0B) : (32M + 1024K)bit x 8 bit
- X16 device(K9F5616X0B) : (16M + 512K)bit x 16bit
- Data Register
- X8 device(K9F5608X0B) : (512 + 16)bit x 8bit
- X16 device(K9F5616X0B) : (256 + 8)bit x16bit
•
Automatic Program and Erase
- Page Program
- X8 device(K9F5608X0B) : (512 + 16)Byte
- X16 device(K9F5616X0B) : (256 + 8)Word
- Block Erase :
- X8 device(K9F5608X0B) : (16K + 512)Byte
- X16 device(K9F5616X0B) : ( 8K + 256)Word
•
Page Read Operation
- Page Size
- X8 device(K9F5608X0B) : (512 + 16)Byte
- X16 device(K9F5616X0B) : (256 + 8)Word
- Random Access
: 10µs(Max.)
- Serial Page Access : 50ns(Min.)
•
Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance
: 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Intelligent Copy-Back
•
Unique ID for Copyright Protection
•
Package
- K9F56XXU0B-YCB0/YIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
- K9F56XXX0B-DCB0/DIB0
63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- K9F5608U0B-VCB0/VIB0
48 - Pin WSOP I (12X17X0.7mm)
- K9F56XXU0B-PCB0/PIB0
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) - Pb-free Package
- K9F56XXX0B-HCB0/HIB0
63- Ball TBGA ( 9 x 11 /0.8mm pitch , Width 1.0 mm)
- Pb-free Package
- K9F5608U0B-FCB0/FIB0
48 - Pin WSOP I (12X17X0.7mm) - Pb-free Package
* K9F5608U0B-V,F(WSOPI ) is the same device as
K9F5608U0B-Y,P(TSOP1) except package type.
GENERAL DESCRIPTION
Offered in 32Mx8bit or 16Mx16bit, the K9F56XXX0B is 256M bit with spare 8M bit capacity. The device is offered in 1.8V or 3.3V
Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be
performed in typical 200µs on the 528-byte(X8 device) or 264-word(X16 device) page and an erase operation can be performed in
typical 2ms on a 16K-byte(X8 device) or 8K-word(X16 device) block. Data in the page can be read out at 50ns cycle time per
byte(X8 device) or word(X16 device).The I/O pins serve as the ports for address and data input/output as well as command input.
The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verifica-
tion and margining of data. Even the write-intensive systems can take advantage of the K9F56XXX0B′s extended reliability of 100K
program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The K9F56XXX0B is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable
applications requiring non-volatility.
3
K9F5608Q0B
K9F5608U0B
K9F5616Q0B
K9F5616U0B
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9F56XXU0B-YCB0,PCB0/YIB0,PIB0
X16
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
X8
N.C
N.C
N.C
N.C
N.C
GND
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
X8
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
X16
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
N.C
N.C
Vcc
N.C
N.C
N.C
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
0.10
MAX
0.004
#48
( 0.25 )
0.010
12.40
0.488 MAX
#24
#25
1.00
±0.05
0.039
±0.002
0.25
0.010 TYP
18.40
±0.10
0.724
±0.004
+0.075
20.00
±0.20
0.787
±0.008
0.20
-0.03
+0.07
#1
0.008
-0.001
0.16
-0.03
+0.07
+0.003
0.50
0.0197
12.00
0.472
0.05
0.002 MIN
0.125
0.035
0~8°
0.45~0.75
0.018~0.030
( 0.50 )
0.020
4
0.005
-0.001
+0.003
1.20
0.047MAX
K9F5608Q0B
K9F5608U0B
K9F5616Q0B
K9F5616U0B
K9F56XXX0B-DCB0,HCB0/DIB0,HIB0
X16
DNU DNU
DNU DNU
/WP
NC
NC
NC
NC
NC
NC
Vss
ALE
/RE
NC
NC
NC
I/O0
I/O1
I/O2
Vss
CLE
NC
NC
NC
NC
NC
/CE
NC
NC
NC
NC
NC
VccQ
/WE
NC
NC
NC
NC
NC
I/O5
I/O6
R/B
NC
NC
NC
NC
Vcc
I/O7
Vss
FLASH MEMORY
PIN CONFIGURATION (TBGA)
X8
DNU DNU
DNU
DNU DNU
DNU
/WP
NC
NC
NC
NC
ALE
/RE
NC
NC
NC
Vss
CLE
NC
NC
NC
/CE
NC
NC
NC
I/O5
/WE
NC
NC
NC
I/O7
R/B
NC
NC
NC
NC
Vcc
DNU DNU
DNU DNU
I/O8 I/O1 I/O10 I/O12 IO14
I/O0
Vss
I/O9 I/O3 VccQ I/O6 I/O15
I/O2 I/O11 I/O4 I/O13 Vss
I/O3 I/O4
DNU DNU
DNU DNU
DNU DNU
DNU DNU
DNU DNU
DNU DNU
DNU DNU
DNU DNU
(Top View)
(Top View)
PACKAGE DIMENSIONS
63-Ball TBGA (measured in millimeters)
Top View
Bottom View
9.00
±0.10
0.80 x9= 7.20
0.80 x5= 4.00
9.00
±0.10
(Datum A)
A
6
5
0.80
4
3
2
1
B
#A1
A
B
0.80 x7= 5.60
2.00
0.32
±0.05
0.45
±0.05
0.90
±0.10
(Datum B)
0.80
C
D
E
2.80
F
G
H
0.80 x11= 8.80
11.00
±0.10
63-∅0.45
±0.05
∅
0.20
M
A B
Side View
9.00
±0.10
0.08MAX
5
11.00
±0.10
京公网安备 11010802033920号
EEWORLD
