YSS901 datasheet, PDF - EEWORLD Datasheet

YSS901

SD

Stereo dipole

Preliminary

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Outline

YSS901 is a device that uses the stereo dipole system (SD) with which the transaural system can be constructed.

When a stereophonic signal that has been processed with the SD system of this device is inputted to two

speakers located adjacently at the center of the field (or to two speakers contained in one cabinet), the virtual

sound positioning function of this system produces the stereophonic sound similar to the one that can be

obtained by using an ordinary stereophonic sound replay system through the central two speakers.

YSS901 has built-in one bit Delta-Sigma type A/D and D/A converters for each of the two channels at its input

and output respectively. Thanks to these built-in converters, this device can process analog stereophonic sound

signal through the converters in addition to digital stereophonic sound signal.

This device performs an advanced convolution through DSP using the FIR filter.

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Features

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Two channel virtual sound positioning by using the stereo dipole system.

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Processes analog or digital signals at each of the two channels.

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Four types of digital data format are available, including 48 fs Serial-DAC16, 18 and 20 bits, and 64 fs.

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Six types of parameter coefficients are built in the device. Additional parameter coefficients can be

downloaded externally.

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The parameter control is made through the DC switches or synchronous three-wire serial system.

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Uses a clock of 2.822 MHz from the crystal. External clock can also be used.

n

Has a built-in PLL circuit for generating clock for operation.

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Internal operating frequency of 512 fs.

n

Allows fading in or out the output of the results of the convolution when switching the coefficient.

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Power supply voltage: 5 V

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Si-gate CMOS process.

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64 QFP

YAMAHA CORPORATION

YSS901CATALOG

CATALOG No.: LSI-4SS901A0

1999. 1

2

TSTNO

TSTNI

TST1

XTAL

ROUT

LOUT

DVSS

PLLC

AVSS

TSTCK

EXTAL

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Pin configuration

51

N.C

DVDD

TSTSEL

CSEL2

CSEL1

CSEL0

RESETN

BSFT1

BSFT0

SCK

SI

DVSS

N.C

1

2

3

4

5

6

64

7

8

9

10

11

12

13

14

15

16

17

18

63

62

61

60

59

58

57

56

55

54

53

52

N.C

50

N.C

49

N.C

48

N.C

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

N.C

AVDD

VREF

AIL

AILOUT

AILRET

26

25

24

23

22

21

20

19

AIR

AIROUT

AIRRET

AVSS

DVSS

TST2

N.C

<64QFP TOP VIEW>

YSS901

N.C

CSN

DIN

N.C

DVDD

BCLK

DOUT

DVDD

SYNCN

DSEL2

DSEL1

DSEL0

CTLSEL

YSS901

YSS901

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Pin Description

No. Pin name

5

6

7

8

9

10

11

12

13

14

15

21

22

23

24

25

26

27

28

29

30

31

37

38

39

40

41

42

43

44

45

46

47

53

54

55

56

57

58

59

60

61

62

63

DVDD

CTLSEL

SYNCN

BCLK

CSN

DOUT

DIN

DSEL2

DSEL1

DSEL0

DVDD

TST2

DVSS

AVSS

AIRRET

AIROUT

AIR

AILRET

AILOUT

AIL

VREF

AVDD

LOUT

ROUT

PLLC

AVSS

EXTAL

XTAL

DVSS

TSTCK

TST1

TSTNI

TSTNO

DVDD

TSTSEL

CSEL2

CSEL1

CSEL0

RESETN

BSFT1

BSFT0

SCK

SI

DVSS

I/O

-

I

O

I

-

AO

AI

AO

AI

-

AO

AI

-

I

O

-

I

O

-

I

-

Function

Digital signal power supply : +5 V

Selection of control method

Digital input/output synchronization signal

Digital input/output bit clock

Serial control interface chip select signal

Digital signal output

Digital signal input

Analog/digital input selection

Digital input/output format selection

Digital signal power supply : +5 V

Test (To be open.)

Digital signal ground

Analog signal ground

Right channel analog signal input return

Right channel analog signal input out

Right channel analog signal input

Left channel analog signal input return

Left channel analog signal input out

Left channel analog signal input

Analog signal VREF

Analog signal power supply : +5 V

Left channel analog signal output

Right channel analog signal output

PLL auxiliary input

Analog signal ground

Crystal clock input

Crystal clock output

Digital signal ground

Test (Connect with DVSS.)

Test (To be open.)

Test (Connect with DVSS.)

Test (To be open.)

Digital signal power supply: +5 V

Test (Connect with DVSS.)

Coefficient selection (Enabled when CTLSEL = 0)

Reset signal input

Bit shift selection (Enabled when CTLSEL = 0)

Serial control interface clock input

Serial control interface data input

Digital signal ground

Notes:

1. Pins of No. 1 to 4, 16 to 20, 32 to 36, 48 to 52 and 64 are to be open.

2.

I: input pin

O: output pin

AI: analog signal input pin

AO: analog output pin.

3

4

SI

CSN

SCK

XTAL

PLLC

EXTAL

CSEL0

CSEL1

CSEL2

BSFT0

BSFT1

RESETN

CTLSEL

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Block Diagram

Timing

stereo dipole

COEF

Serial

Control

AIL

AILOUT

Lch

AILRET

LOUT

AIR

Lch

AD

COEF 1

COEF 2

DA

ROUT

AIROUT

AIRRET

Rch

Bit

Shift

COEF 2

Fader

SYNCN

Rch

COEF 1

Rch

Digital

Out

DOUT

BCLK

Digital

In

DIN

Noise Gate

(Input Level Check)

NGO

VREF

AVSS

AVDD

DVSS

DVDD

YSS901

DSEL0

DSEL1

DSEL2

NGATE

YSS901

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Outline of Functions

1. Clock signals

XTAL, EXTAL

and

PLLC

For the clock signal, use the crystal connected to XTAL EXTAL pin with which the clock signal is obtained by the

self-oscillation at the crystal oscillation circuit, or external signal supplied through EXTAL pin. The frequency of the

clock obtained by the self-oscillation is 2.822 MHz (or 44.1 kHz * 64). The internal operation is carried out with 512

fs clock that is made by the PLL.

Insert an analog filter in between PLLC and GND pins.

2. Data input/output signals

Analog/digital input selection pin:

DSEL2

This pin is used to select a type of the input signal. DSEL2 = 0 selects the digital signal input, or DSEL2 = 1 selects

the analog signal input.

2-1) Digital signal

Digital signal input/output pins:

DIN, BCLK, SYNCN

and

DOUT

Digital signals should be inputted through DIN, BCLK and SYNCN pins.

DIN signal (PCM data) must be in synchronous with BCLK (bit clock) and SYNCN (word clock) signals.

Digital signal is outputted from DOUT pin.

Input/output format designation pins:

DSEL1

and

DSEL0

These pins are used to designate a data format for DAC. The settings of DSEL1 and DSEL0 and their output formats

are as follows.

DSEL1

0

1

DSEL0

0

1

0

1

DAC output format

48 fs 16 bits Data LSB justified

48 fs 18 bits Data LSB justified (Bits 1 and 0 are “0”.)

48 fs 20 bits Data LSB justified (Bits 3 through 0 are “0”.)

64 fs 16 bits Data MSB justified (Delay by one bit)

For the details of the format, refer to “Serial Data Interface” explained later in this document.

2-2) Analog signal

Analog input/output pins:

AIL, AILOUT, AILRET, LOUT, AIR, AIROUT, AIRRET

and

ROUT

Analog signals should be inputted through AIL and AIR pins. The signals that have been processed by the stereo

dipole (SD) are outputted from LOUT and ROUT pins respectively. Add an analog filter circuit, an example of

which is shown later in this document.

Center voltage pin

VREF

This pin outputs a reference voltage for analog signal processing. Connect an appropriate capacitor between VREF

and GND pins.

3. Controlling functions

3-1) Control method selection pin:

CTLSEL

This pin is used for selection of a control method as described below.

CTLSEL = 0 : Selection of CSEL2, CSEL1 or CSEL0 by means of DC switch (H/L) is enabled.

CTLSEL = 1 : Selection of CSN, SI or SCK through the microcomputer is enabled.

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YSS901

YSS901 Overview

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