BX80638I53360M/SR0MV datasheet, PDF

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BX80638I53360M/SR0MV: DescriptionRISC Microprocessor, 64-Bit, 3500MHz, CMOS, PPGA988; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，172 Pages; ManufacturerIntel; Websitehttp://www.intel.com/; Environmental Compliance

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BX80638I53360M/SR0MV Overview

RISC Microprocessor, 64-Bit, 3500MHz, CMOS, PPGA988

BX80638I53360M/SR0MV Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	114109617
Reach Compliance Code	unknown
bit size	64
JESD-30 code	R-PPGA-P988
Number of terminals	988
Package body material	PLASTIC
encapsulated code	PGA
Encapsulate equivalent code	PGA988,35X36,40
Package shape	RECTANGULAR
Package form	GRID ARRAY
power supply	0.3/1.52 V
Certification status	Not Qualified
speed	3500 MHz
Maximum slew rate	97500 mA
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	1 mm
Terminal location	PERPENDICULAR
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Mobile 3rd Generation Intel

Core™

Processor Family, Mobile Intel

Pentium

Processor Family, and

Mobile Intel

Celeron

Processor

Family

Datasheet, Volume 1 of 2

June 2013

Document Number: 326768-006

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER

AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING

LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal

injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU

SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS,

OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE

ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH

ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS

NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the

absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future

definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The

information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

This document contains information on products in the design phase of development. Do not finalize a design with this information.

Revised information will be published when the product is available. Verify with your local sales office that you have the latest

datasheet before finalizing a design.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained

by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.

Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting

operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.

Enhanced Intel SpeedStep

Technology; See the Processor Spec Finder or contact your Intel representative for more information.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device

drivers and applications enabled for Intel

64 architecture. Performance will vary depending on your hardware and software

configurations. Consult with your system vendor for more information.

No computer system can provide absolute security under all conditions. Intel

Trusted Execution Technology (Intel

TXT) requires

a computer system with Intel

Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code

Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor,

an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing

Group and specific software for some uses. For more information, see

http://www.intel.com/technology/security/.

Intel

Virtualization Technology requires a computer system with an enabled Intel

processor, BIOS, virtual machine monitor

(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary

depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible

with all operating systems. Please check with your application vendor.

Intel

Active Management Technology requires the computer system to have an Intel® AMT-enabled chipset, network hardware

and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the

purchaser and may require scripting with the management console or further integration into existing security frameworks to

enable certain functionality. It may also require modifications of implementation of new business processes. With regard to

notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting

wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see

http://www.intel.com/technology/

platform-technology/intel-amt/.

Intel

Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost

Technology performance varies depending on hardware, software and overall system configuration. Check with your PC

manufacturer on whether your system delivers Intel Turbo Boost Technology.For more information, see http://www.intel.com/

technology/turboboost.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,

not across different processor families. See

www.intel.com/products/processor_number for details.

Intel, Intel Core, Pentium, Celeron, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet, Volume 1

Contents

Introduction

............................................................................................................ 11

1.1

Processor Feature Details ................................................................................... 13

1.1.1 Supported Technologies .......................................................................... 13

1.2

Interfaces ........................................................................................................ 13

1.2.1 System Memory Support ......................................................................... 13

1.2.2 PCI Express* ......................................................................................... 14

1.2.3 Direct Media Interface (DMI).................................................................... 15

1.2.4 Platform Environment Control Interface (PECI) ........................................... 16

1.2.5 Processor Graphics ................................................................................. 16

1.2.6 Embedded DisplayPort* (eDP*) ................................................................ 17

1.2.7 Intel

Flexible Display Interface (Intel

FDI) ............................................. 17

1.3

Power Management Support ............................................................................... 17

1.3.1 Processor Core....................................................................................... 17

1.3.2 System ................................................................................................. 17

1.3.3 Memory Controller.................................................................................. 17

1.3.4 PCI Express* ......................................................................................... 17

1.3.5 Direct Media Interface (DMI).................................................................... 17

1.3.6 Processor Graphics Controller (GT) ........................................................... 18

1.3.7 Thermal Management Support ................................................................. 18

1.4

Processor Family SKU Definition .......................................................................... 18

1.5

Package ........................................................................................................... 19

1.6

Processor Compatibility ...................................................................................... 19

1.7

Terminology ..................................................................................................... 21

1.8

Related Documents ........................................................................................... 24

Interfaces................................................................................................................

2.1

System Memory Interface .................................................................................. 25

2.1.1 System Memory Technology Supported ..................................................... 25

2.1.2 System Memory Timing Support............................................................... 26

2.1.3 System Memory Organization Modes......................................................... 27

2.1.3.1 Single-Channel Mode................................................................. 27

2.1.3.2 Dual-Channel Mode – Intel

Flex Memory Technology Mode ........... 27

2.1.4 Rules for Populating Memory Slots ............................................................ 28

2.1.5 Technology Enhancements of Intel

Fast Memory Access (Intel

FMA).......... 29

2.1.5.1 Just-in-Time Command Scheduling.............................................. 29

2.1.5.2 Command Overlap .................................................................... 29

2.1.5.3 Out-of-Order Scheduling ............................................................ 29

2.1.6 Data Scrambling .................................................................................... 29

2.1.7 DRAM Clock Generation........................................................................... 29

2.1.8 DDR3 Reference Voltage Generation ......................................................... 30

2.2

PCI Express* Interface....................................................................................... 30

2.2.1 PCI Express* Architecture ....................................................................... 30

2.2.1.1 Transaction Layer ..................................................................... 31

2.2.1.2 Data Link Layer ........................................................................ 31

2.2.1.3 Physical Layer .......................................................................... 31

2.2.2 PCI Express* Configuration Mechanism ..................................................... 32

2.2.3 PCI Express* Graphics ............................................................................ 33

2.2.3.1 PCI Express* Lanes Connection .................................................. 33

2.3

Direct Media Interface (DMI)............................................................................... 33

2.3.1 DMI Error Flow....................................................................................... 34

2.3.2 Processor / PCH Compatibility Assumptions................................................ 34

Datasheet, Volume 1

2.4

2.5

2.6

2.3.3 DMI Link Down .......................................................................................34

Processor Graphics Controller (GT).......................................................................35

2.4.1 3D and Video Engines for Graphics Processing ............................................35

2.4.1.1 3D Engine Execution Units ..........................................................35

2.4.1.2 3D Pipeline ...............................................................................36

2.4.1.3 Video Engine ............................................................................36

2.4.1.4 2D Engine ................................................................................37

2.4.2 Processor Graphics Display ......................................................................38

2.4.2.1 Display Planes ..........................................................................38

2.4.2.2 Display Pipes ............................................................................39

2.4.2.3 Display Ports ............................................................................39

2.4.2.4 Embedded DisplayPort* (eDP*) ...................................................39

2.4.3 Intel

Flexible Display Interface (Intel

FDI) .............................................39

2.4.4 Multi Graphics Controllers Multi-Monitor Support .........................................40

Platform Environment Control Interface (PECI) ......................................................40

Interface Clocking..............................................................................................40

2.6.1 Internal Clocking Requirements ................................................................40

Technologies............................................................................................................41

3.1

Intel

Virtualization Technology (Intel

VT) ..........................................................41

3.1.1 Intel

Virtualization Technology (Intel

VT) for

IA-32, Intel

64 and Intel

Architecture

(Intel

VT-x) Objectives ..........................................................................41

3.1.2 Intel

Virtualization Technology (Intel

VT) for

IA-32, Intel

64 and Intel

Architecture

(Intel

VT-x) Features ............................................................................42

3.1.3 Intel

Virtualization Technology (Intel

VT) for Directed

I/O (Intel

VT-d) Objectives ....................................................................42

3.1.4 Intel

Virtualization Technology (Intel

VT) for Directed

I/O (Intel

VT-d) Features.......................................................................43

3.1.5 Intel

Virtualization Technology (Intel

VT) for Directed

I/O (Intel

VT-d) Features Not Supported..................................................43

Trusted Execution Technology (Intel

TXT) .................................................44

3.2

Intel

3.3

Intel

Hyper-Threading Technology (Intel

HT Technology) ....................................44

3.4

Intel

Turbo Boost Technology ............................................................................45

3.4.1 Intel

Turbo Boost Technology Frequency...................................................45

3.4.2 Intel

Turbo Boost Technology Graphics Frequency.....................................46

3.5

Intel

Advanced Vector Extensions (Intel

AVX)....................................................46

3.6

Security and Cryptography Technologies...............................................................46

3.6.1 Intel

Advanced Encryption Standard New Instructions (Intel

AES-NI) ........46

3.6.2 PCLMULQDQ Instruction ..........................................................................47

3.6.3 RDRAND Instruction ................................................................................47

3.7

Intel

64 Architecture x2APIC .............................................................................47

3.8

Supervisor Mode Execution Protection (SMEP) .......................................................48

3.9

Power Aware Interrupt Routing (PAIR)..................................................................49

Power Management

.................................................................................................51

4.1

Advanced Configuration and Power Interface

(ACPI) States Supported.....................................................................................52

4.1.1 System States........................................................................................52

4.1.2 Processor Core / Package Idle States.........................................................52

4.1.3 Integrated Memory Controller States .........................................................52

4.1.4 PCI Express* Link States .........................................................................53

4.1.5 Direct Media Interface (DMI) States ..........................................................53

4.1.6 Processor Graphics Controller States .........................................................53

4.1.7 Interface State Combinations ...................................................................53

4.2

Processor Core Power Management ......................................................................54

Datasheet, Volume 1

4.3

4.4

4.5

4.6

4.7

Enhanced Intel

SpeedStep

Technology.................................................. 54

Low-Power Idle States ............................................................................ 55

Requesting Low-Power Idle States ............................................................ 56

Core C-states ........................................................................................ 57

4.2.4.1 Core C0 State........................................................................... 57

4.2.4.2 Core C1 / C1E State .................................................................. 57

4.2.4.3 Core C3 State........................................................................... 57

4.2.4.4 Core C6 State........................................................................... 57

4.2.4.5 Core C7 State........................................................................... 58

4.2.4.6 C-State Auto-Demotion ............................................................. 58

4.2.5 Package C-States ................................................................................... 58

4.2.5.1 Package C0 .............................................................................. 60

4.2.5.2 Package C1/C1E ....................................................................... 60

4.2.5.3 Package C3 State...................................................................... 60

4.2.5.4 Package C6 State...................................................................... 60

4.2.5.5 Package C7 State...................................................................... 61

4.2.5.6 Dynamic L3 Cache Sizing ........................................................... 61

Integrated Memory Controller (IMC) Power Management ........................................ 61

4.3.1 Disabling Unused System Memory Outputs ................................................ 61

4.3.2 DRAM Power Management and Initialization ............................................... 62

4.3.2.1 Initialization Role of CKE ............................................................ 63

4.3.2.2 Conditional Self-Refresh ............................................................ 63

4.3.2.3 Dynamic Power Down Operation ................................................. 64

4.3.2.4 DRAM I/O Power Management .................................................... 64

4.3.3 DDR Electrical Power Gating (EPG) ........................................................... 64

PCI Express* Power Management ........................................................................ 65

DMI Power Management..................................................................................... 65

Graphics Power Management .............................................................................. 65

4.6.1 Intel

Rapid Memory Power Management (Intel

RMPM)

(also known as CxSR) ............................................................................. 65

4.6.2 Intel

Graphics Performance Modulation Technology (Intel

GPMT) .............. 65

4.6.3 Graphics Render C-State ......................................................................... 66

4.6.4 Intel

Smart 2D Display Technology (Intel

S2DDT) .................................. 66

4.6.5 Intel

Graphics Dynamic Frequency.......................................................... 66

4.6.6 Display Power Savings Technology 6.0 (DPST) ........................................... 67

4.6.7 Automatic Display Brightness (ADB) ......................................................... 67

4.6.8 Intel

Seamless Display Refresh Rate Switching

Technology (Intel

SDRRS Technology) .................................................... 67

Graphics Thermal Power Management .................................................................. 68

4.2.1

4.2.2

4.2.3

4.2.4

Thermal Management

.............................................................................................. 69

5.1

Thermal Considerations...................................................................................... 69

5.2

Intel

Turbo Boost Technology Power Monitoring................................................... 70

5.3

Intel

Turbo Boost Technology Power Control ....................................................... 70

5.3.1 Package Power Control............................................................................ 70

5.3.2 Power Plane Control................................................................................ 72

5.3.3 Turbo Time Parameter ............................................................................ 72

5.4

Configurable Thermal Design Power (cTDP) and

Low Power Mode (LPM) ...................................................................................... 72

5.4.1 Configurable TDP (cTDP) ......................................................................... 72

5.4.2 Low Power Mode .................................................................................... 73

5.5

Thermal and Power Specifications........................................................................ 74

5.6

Thermal Management Features ........................................................................... 77

5.6.1 Adaptive Thermal Monitor........................................................................ 77

5.6.1.1 TCC Activation Offset ................................................................ 78

5.6.1.2 Frequency / Voltage Control ....................................................... 78

5.6.1.3 Clock Modulation ...................................................................... 80

Datasheet, Volume 1

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