5962F9670401VXX datasheet, PDF

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5962F9670401VXX: DescriptionAC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERAMIC, FP-16; Categorylogic logic; File Size10KB，1 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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5962F9670401VXX Overview

AC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16, CERAMIC, FP-16

5962F9670401VXX Parametric

Parameter Name	Attribute value
Objectid	1515922267
Parts packaging code	DFP
package instruction	DFP,
Contacts	16
Reach Compliance Code	unknown
series	AC
JESD-30 code	R-CDFP-F16
JESD-609 code	e4
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
propagation delay (tpd)	21 ns
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	FLAT
Terminal location	DUAL
total dose	300k Rad(Si) V
Trigger type	NEGATIVE EDGE
minfmax	35 MHz

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ACS112MS

January 1996

Radiation Hardened

Dual J-K Flip-Flop

Pinouts

16 PIN CERAMIC DUAL-IN-LINE

MIL-STD-1835, DESIGNATOR CDIP2-T16,

LEAD FINISH C

TOP VIEW

CP1 1

K1 2

J1 3

S1 4

Q1 5

Q1 6

Q2 7

GND 8

16 VCC

15 R1

14 R2

13 CP2

12 K2

11 J2

10 S2

9 Q2

Features

• Devices QML Qualiﬁed in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in

SMD# 5962-96704 and Intersil’sIntersil QM Plan

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x 10

-10

Errors/Bit/Day

(Typ)

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm

/mg

• Dose Rate Upset . . . . . . . . . . . . . . . . >10

RAD (Si)/s, 20ns Pulse

• Dose Rate Survivability . . . . . . . . . . . >10

RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55

C to +125

• Signiﬁcant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

• Input Logic Levels

- VIL = 30% of VCC Max

- VIH = 70% of VCC Min

• Input Current

≤

1µA at VOL, VOH

• Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)

16 PIN CERAMIC FLATPACK

MIL-STD-1835, DESIGNATOR CDFP4-F16,

LEAD FINISH C

TOP VIEW

CP1

GND

VCC

CP2

Description

The Intersil ACS112MS is a Radiation Hardened Dual J-K Flip-Flop with

Set and Reset. The output change states on the negative transition of

the clock (CP1N or CP2N).

The ACS112MS utilizes advanced CMOS/SOS technology to achieve

high-speed operation. This device is a member of the radiation hard-

ened, high-speed, CMOS/SOS Logic Family.

The ACS112MS is supplied in a 16 lead Ceramic Flatpack (K sufﬁx) or a

Ceramic Dual-In-Line Package (D sufﬁx).

Ordering Information

PART NUMBER

5962F9670401VEC

5962F9670401VXC

ACS112D/Sample

ACS112K/Sample

ACS112HMSR

TEMPERATURE RANGE

-55

C to +125

-55

C to +125

SCREENING LEVEL

MIL-PRF-38535 Class V

Sample

Die

PACKAGE

16 Lead SBDIP

16 Lead Ceramic Flatpack

16 Lead SBDIP

16 Lead Ceramic Flatpack

Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

Intersil Corporation 1999

Spec Number

File Number

518816

3571.1

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