5962R9573801VEC datasheet, PDF

5962R9573801VEC: DescriptionHCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16; Categorylogic logic; File Size223KB，9 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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5962R9573801VEC Overview

HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16

Parameter Name	Attribute value
Objectid	1532325290
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16
Reach Compliance Code	unknown
series	HCT
JESD-30 code	R-CDIP-T16
JESD-609 code	e4
length	19.05 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	J-K FLIP-FLOP
Maximum Frequency@Nom-Sup	20000000 Hz
MaximumI(ol)	0.004 A
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Prop。Delay @ Nom-Sup	42 ns
propagation delay (tpd)	42 ns
Certification status	Not Qualified
Filter level	38535V;38534K;883S
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
total dose	100k Rad(Si) V
Trigger type	NEGATIVE EDGE
width	7.62 mm

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