BiCMOS Static RAM
240K (16K x 15-Bit)
Cache-Tag RAM
for PowerPC™ and RISC Processors
Features
x
x
x
x
x
x
x
x
x
x
x
x
IDT71216
16K x 15 Configuration
– 12 TAG Bits
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
Match output uses Valid bit to qualify MATCH output
High-Speed Address-to-Match comparison times
– 8/9/10/12ns over commercial temperature range
TA
circuitry included inside the Cache-Tag for highest
speed operation
Asynchronous Read/Match operation with Synchronous
Write and Reset operation
Separate
WE
for the TAG bits and the Status bits
Separate
OE
for the TAG bits, the Status bits, and
TA
Synchronous
RESET
pin for invalidation of all Tag
entries
Dual Chip selects for easy depth expansion with no
performance degredation
I/O pins both 5V TTL and 3.3V LVTTL compatible with
V
CCQ
pins
PWRDN
pin to place device in low-power mode
Packaged in a 80-pin plastic Thin Quad Flat Pack (TQFP).
Description
The IDT71216 is a 245,760-bit Cache Tag Static RAM, orga-
nized 16K x 15 and designed to support PowerPC and other RISC
processors at bus speeds up to 66MHz. There are twelve common
I/O TAG bits, with the remaining three bits used as status bits. A 12-
bit comparator is on-chip to allow fast comparison of the twelve
stored TAG bits and the current Tag input data. An active HIGH
MATCH output is generated when these two groups of data are the
same for a given address. This high-speed MATCH signal, with t
ADM
as fast as 8ns, provides the fastest possible enabling of secondary
cache accesses.
The three separate I/O status bits (VLD, DTY, and WT) can be
configured for either dedicated or generic functionality, depending on
the SFUNC input pin. With SFUNC LOW, the status bits are defined
and used internally by the device, allowing easier determination of
the validity and use of the given Tag data. SFUNC HIGH releases the
defined internal status bit usage and control, allowing the user to
configure the status bit information to fit his system needs. A synchro-
nous
RESET
pin, when held LOW at a rising clock edge, will reset all
status bits in the array for easy invalidation of all Tag addresses.
The IDT71216 also provides the option for Transfer Acknowledge
(TA) generation within the cache tag itself, based upon MATCH, VLD
bit, WT bit, and external inputs provided by the user. This can
significantly simplify cache controller logic and minimize cache
decision time. Match and Read operations are both asynchronous
in order to provide the fastest access times possible, while Write
operations are synchronous for ease of system timing.
The IDT71216 uses a 5V power supply on Vcc, with separate
V
CCQ
pins provided for the outputs to offer compliance with both 5V
TTL and 3.3V LVTTL Logic levels. The
PWRDN
pin offers a low-
power standby mode to reduce power consumption by 90%, provid-
ing significant system power savings.
The IDT71216 is fabricated using IDT’s high-performance, high-
reliability BiCMOS technology and is offered in a space-saving 80-
pin plastic Thin Quad Flat Pack (TQFP) package.
Pin Descriptions
A
0
– A
13
CS1,
CS2
WET
WES
OET
OES
RESET
PWRDN
SFUNC
TT1
VLD
IN
/S
1IN
DTY
IN
/S
2IN
WT
IN
/S
3IN
Address Inputs
Chip Selects
Write Enable – Tag Bits
Write Enable – Status Bits
Output Enable – Tag Bits
Output Enable – Status Bits
Status Bit Reset
Pow erdown Mode Control Pin
Status Bit Function Control Pin
Input
Input
Input
Input
Input
Input
Input
Input
Input
CLK
TAH
TAOE
TAIN
TA
TAG
0
– TAG
11
VLD
OUT
/S
1OUT
DTY
OUT
/S
2OUT
WT
OUT
/S
3OUT
MATCH
V
CC
V
CCQ
V
SS
System Clock
TA
Force High
TA
Output Enable
Additional
TA
Input
Transfer Acknowledge
Tag Data Input/Outputs
Valid Bit/S
1
Bit Output
Dirty Bit/S
2
Bit Output
Write Through Bit/S
3
Bit Output
Match
+5V Power
Output Buffer Power
Ground
Input
Input
Input
Input
Output
I/O
Output
Output
Output
Output
Pwr
QPwr
Gnd
3067 tbl 01
Read/Write Input from Processor Input
Valid Bit/S
1
Bit Input
Dirty Bit/S
2
Bit Input
Write Through Bit/S
3
Bit Input
Input
Input
Input
PowerPC is a trademark of International Business Machines, Inc.
OCTOBER 1999
1
DSC-3067/04
©1999 Integrated Device Technology, Inc.
IDT71216 BiCMOS Static RAM
240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors
Commercial Temperature Range
Truth Tables Chip Select, Reset, and Power-Down Functions
(1,2)
CS1
CS2
RESET PWRDN
CLK
WET WES
TAOE
TAG
VLD
OUT
DTY
OUT
WT
OUT
MATCH
TA
OPERATION
POWER
CHIP SELECT FUNCTION
H
X
L
X
L
H
X
X
X
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
Hi-Z
Hi-Z
—
Deselected
Deselected
Selected
Active
Active
Active
RESET FUNCTION
L
L
H
X
X
X
H
H
X
L
X
X
L
L
L
L
L
L
H
H
H
H
H
H
↑
↑
↑
↑
↑
↑
H
H
H
H
L
X
H
H
H
H
X
L
L
H
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
—
L
(3)
L
(3)
Hi-Z
Hi-Z
—
—
L
(3)
L
(3)
Hi-Z
Hi-Z
—
—
L
(3)
L
(3)
Hi-Z
Hi-Z
—
—
L
(3)
L
(3)
Hi-Z
Hi-Z
—
—
H
Hi-Z
Hi-Z
Hi-Z
—
—
Reset Status
Reset Status
Reset Status
Reset Status
Not Allowed
Not Allowed
Active
Active
Active
Active
—
—
POWER-DOWN FUNCTION
X
X
X
L
X
H
H
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Power-down
Standby
3067 tbl 02
NOTES:
1. "H" = V
IH
, "L" = V
IL
, "X" = don't care, "–" = unrelated.
2.
OET, OES,
TT1, TAH,
TAIN
and SFUNC are "X" for this table.
3.
OES
is LOW.
Truth Tables Read and Write Functions
(1,2)
OET
OES
WET
WES
CLK
TT1
TAG
VLD
IN
DTY
IN
WT
IN
VLD
OUT
DTY
OUT
WT
OUT
MATCH
OPERATION
READ FUNCTION
L
X
H
X
X
L
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D
OUT
—
Hi-Z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
OUT
—
Hi-Z
—
D
OUT
—
Hi-Z
—
D
OUT
—
Hi-Z
D
OUT
D
OUT
D
OUT
D
OUT
Read TAG I/O
Read Status Bits
TAG I/O Disable
Status Disabled
WRITE FUNCTION
H
L
X
X
X
X
L
H
L
L
X
X
X
X
L
L
↑
↑
↑
↑
X
X
X
X
D
IN
—
—
—
—
—
D
IN
D
IN
—
—
D
IN
D
IN
—
—
D
IN
D
IN
D
OUT
—
D
OUT
(3)
Hi-Z
D
OUT
—
D
OUT
(3)
Hi-Z
D
OUT
—
D
OUT
(3)
Hi-Z
L
—
L
L
Write TAG I/O
Not Allowed
Write Status Bits
Write Status Bits
3067 tbl 03
NOTES:
1. "H" = V
IH
, "L" = V
IL
, "X" = don't care, "–" = unrelated.
2. This table applies when
CS1
is LOW and CS2,
RESET,
and
PWRDN
are HIGH.
TAOE,
TAH,
TAIN
and SFUNC are "X" for this table.
3. D
OUT
in this case is the same as D
IN
; that is, the input data is written through to the outputs during the write operation.
6.42
4
IDT71216 BiCMOS Static RAM
240K (16K x 15-Bit) Cache-Tag RAM for PowerPC™ and RISC Processors
Commercial Temperature Range
Truth Table Match Function
(1,2,3)
CS1
H
X
L
L
L
L
L
L
L
CS2
X
L
H
H
H
H
H
H
H
SFUNC
X
X
X
X
X
X
L
L
H
OET
X
X
X
L
H
X
H
H
H
WET
X
X
X
H
L
X
H
H
H
WES
X
X
X
X
X
L
H
H
H
TAG
Hi-Z
Hi-Z
—
D
OUT
D
IN
—
TAG
IN
TAG
IN
TAG
IN
VLD
(4)
—
—
—
—
—
D
IN
L
H
X
DTY
(4)
—
—
—
—
—
D
IN
—
—
—
WT
(4)
—
—
—
—
—
D
IN
—
—
—
MATCH
Hi-Z
Hi-Z
D
OUT
L
L
L
L
M
M
OPERATION
Deselected
Deselected
Selected
Read Tag I/O
Write Tag I/O
Write Status Bits
Invalid Data — Dedicated Status Bits
Match — Dedicated Status Bits
Match — Generic Status Bits
3067 tbl 04
NOTES:
1. "H" = V
IH
, "L" = V
IL
, "X" = don't care, "–" = unrelated.
2. M = HIGH if TAG
IN
equals the memory contents at that address; M = LOW if TAG
IN
does not equal the memory contents at that address.
3.
PWRDN
and
RESET
are HIGH for this table. TT1, TAH,
TAOE, TAIN, OES,
and CLK are "X".
4. This column represents the stored memory cell data for the given Status bit at the selected address.
Truth Table
TA
Function
(1,2,3,5)
TAOE
H
L
L
L
L
L
L
L
L
L
L
L
TAIN
(6)
X
L
H
H
H
H
H
H
H
H
H
H
OET
X
X
L
X
X
X
X
X
H
H
H
H
WET
X
X
X
L
X
X
X
X
H
H
H
H
WES
X
X
X
X
L
X
X
X
H
H
H
H
TAH
X
X
X
X
X
H
X
X
L
L
L
L
TT1
X
X
X
X
X
X
X
L
X
H
X
X
SFUNC
X
X
X
X
X
X
L
L
L
L
L
H
VLD
(4)
DTY
(4)
WT
(4)
X
X
X
X
D
IN
X
L
X
H
H
H
X
—
—
—
—
D
IN
—
—
—
—
—
—
—
X
X
X
X
D
IN
X
X
H
L
X
X
X
TAG
—
—
D
OUT
D
IN
—
—
—
—
TAG
IN
TAG
IN
TAG
IN
TAG
IN
MATCH
—
X
L
L
L
X
L
X
M
M
M
M
TA
Hi-Z
L
H
H
H
H
H
H
M
M
M
M
OPERATION
TA
Disabled
External
TA
Input
(7)
Read TAG
Write TAG
Write Status
Force
TA
HIGH
Invalid TAG
Write Through
Compare
Compare
Compare
Compare
3067 tbl 05
NOTES:
1. "H" = V
IH
, "L" = V
IL
, "X" = don't care, "–" = unrelated.
2. M = HIGH if TAG
IN
equals the memory contents at that address; M = LOW if TAG
IN
does not equal the memory contents at that address.
3.
PWRDN
and
RESET
are HIGH for this table. CLK and
OES
are "X".
4. This column represents the stored memory cell data for the given Status bit at the selected address.
5.
CS1
is LOW, CS2 is HIGH for this table.
6.
TAIN
is a synchronous input; thus the inputs noted in the table must be applied during a rising CLK edge.
7.
TAIN
will be a factor in determining the
TA
output in all cases except when TAH is HIGH and there is a valid MATCH. In that case,
TA
will be LOW(Valid).
6.42
5
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