PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Features
• Four Pairs of Differential Clocks
• Low skew < 50ps
• Low jitter < 50ps
• Output Enable for all outputs
• Outputs tristate control via SMBus
• Power Management Control
• Programmable PLL Bandwidth
• PLL or Fanout operation
• 3.3V Operation
• Packaging:
- 28-Pin SSOP (H) & 28-Pin TSSOP (L)
- Pb-Free and Green Option (HE and LE)
Description
Pericom Semiconductors PI6C20400 is a high-speed, low-noise
differential clock buffer designed to be companion to PI6C410B.
The device distributes the differential SRC clock from PI6C410B
to four differential pairs of clock outputs either with or without
PLL. The clock outputs are controlled by input selection of
SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When
input of either SRC_STOP# or PWRDWN# is low, the output
clocks are Tristated. When PWRDWN# is low, the SDA and
SCLK inputs must be Tristated.
Block Diagram
OE_INV
OE_0 & OE_3
SRC_STOP#
PWRDWN#
SCLK
SDA
PLL/BYPASS#
SRC
SRC#
Output
Control
Pin Configuration
V
DD
SRC
SCR#
V
SS
V
DD
OUT0
OUT0#
OE_0
OUT1
OUT1#
V
DD
PLL/BYPASS#
SCLK
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT0
OUT0#
OUT0
OUT1#
OUT2
OUT2#
OUT3
OUT3#
SMBus
Controller
PLL_BW#
PLL
DIV
V
DD_A
V
SS_A
I
REF
OE_INV
V
DD
OUT3
OUT3#
OE_3
OUT2
OUT2#
V
DD
PLL_BW#
SRC_STOP#
PWRDWN#
1
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Pin Descriptions
Pin Name
SRC & SRC#
OE_0 & OE_3
Type
Input
Input
2, 3
8, 21
Pin No
Description
0.7V Differential SRC input from PI6C410 clock synthesizer
3.3V LVTTL input for enabling outputs, active high.
OE_0 for OUT0 / OUT0#
OE_3 for OUT3 / OUT3#
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
When 0 = same stage
When 1 = OE_0, OE_3, SRC_STOP#, PWRDWN# inverted.
0.7V Differential outputs
3.3V LVTTL input for selecting fan-out of PLL operation.
SMBus compatible SCLOCK input
SMBus compatible SDATA
External resistor connection to set the differential output current
3.3V LVTTL input for SRC stop, active low
3.3V LVTTL input for selecting the PLL bandwidth
3.3V LVTTL input for Power Down operation, active low
3.3V Power Supply for Outputs
Ground for Outputs
Ground for PLL
3.3V Power Supply for PLL
OE_INV
Input
25
6, 7, 9, 10, 19, 20,
22, 23
12
13
14
26
16
17
15
1, 5, 11, 18, 24
4
27
28
OUT[0:3] & OUT[0:3]#
PLL/BYPASS#
SCLK
SDA
IREF
SRC_STOP#
PLL_BW#
PWRDWN#
V
DD
VSS
VSS_A
VDD_A
Output
Input
Input
I/O
Input
Input
Input
Input
Power
Ground
Ground
Power
Serial Data Interface (SMBus)
PI6C20400 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address assignment
A6
1
A5
1
A4
0
A3
1
A2
1
A1
1
A0
0
R/W
0/1
Data Protocol
1 bit
Start
bit
7 bits
Slave
Addr
1
R/W
1
Ack
8 bits
Register
offset
1
Ack
8 bits
Byte
Count
=N
1
Ack
8 bits
Data
Byte 0
1
Ack
…
8 bits
Data
Byte N
-1
1
Ack
1 bit
Stop
bit
Notes:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
2
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Data Byte 0: Control Register
Bit
0
Descriptions
Outputs Mode
0 = Divide by 2
1 = Normal
PLL/BYPASS#
0 = Fanout
1 = PLL
PLL Bandwidth
0 = High Bandwidth,
1 = Low Bandwidth
TBD
TBD
TBD
SRC_STOP#
0 = Driven when stopped
1 = Tristate
PWRDWN#
0 = Driven when stopped
1 = Tristate
RW
0 = Driven when stopped
OUT[0:3], OUT[0:3]#
Type
RW
Power Up Condition
1 = Normal
Output(s) Affected
OUT[0:3], OUT[0:3]#
Source
Pin
NA
1
RW
1 = PLL
OUT[0:3], OUT[0:3]#
NA
2
3
4
5
6
RW
1 = Low
OUT[0:3], OUT[0:3]#
NA
NA
NA
NA
7
RW
0 = Driven when stopped
OUT[0:3], OUT[0:3]#
NA
Data Byte 1: Control Register
Bit
0
1
2
3
4
5
6
7
OUTPUTS enable
1 = Enabled
0 = Disabled
RW
RW
1 = Enabled
1 = Enabled
OUT2, OUT2#
OUT3, OUT3#
NA
NA
OUTPUTS enable
1 = Enabled
0 = Disabled
RW
RW
1 = Enabled
1 = Enabled
OUT0, OUT0#
OUT1, OUT1#
NA
NA
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
3
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Data Byte 2: Control Register
Bit
0
1
2
3
4
5
6
7
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
RW
RW
0 = Free running
0 = Free running
OUT2, OUT2#
OUT3, OUT3#
NA
NA
Allow control of OUTPUTS with
assertion of SRC_STOP#
0 = Free running
1 = Stopped with SRC_Stop#
RW
RW
0 = Free running
0 = Free running
OUT0, OUT0#
OUT1, OUT1#
NA
NA
Descriptions
Type
Power Up Condition
Output(s) Affected
Source
Pin
Data Byte 3: Control Register
Bit
0
1
2
3
4
5
6
7
TBD
Descriptions
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power Up Condition
Output(s) Affected
Source
Pin
Data Byte 4: Pericom ID Register
Bit
0
1
2
3
4
5
6
7
Pericom ID
Descriptions
Type
R
R
R
R
R
R
R
R
Power Up Condition
0
0
0
0
0
1
0
0
Output(s) Affected
NA
NA
NA
NA
NA
NA
NA
NA
Pin
NA
NA
NA
NA
NA
NA
NA
NA
4
PS8744A
06/23/05
PI6C20400
1:4 Clock Driver for Intel
PCI Express Chipsets
Functionality
PWRDWN#
1
0
OUT
Normal
I
REF
×
2 or Float
OUT#
Normal
Low
SRC_Stop#
1
0
OUT
Normal
I
REF
×
6 or Float
OUT#
Normal
Low
Power Down (PWRDWN# assertion)
PWRDWN#
OUT
OUT#
Figure 1. Power down sequence
Power Down (PWRDWN# De-assertion)
Tstable
<1ms
PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
Figure 2. Power down de-assert sequence
5
PS8744A
06/23/05
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