21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308
3.3V Zero-Delay Buffer
Product Features
•
10 MHz to 134 MHz operating range
•
Zero input-output propagation delay, adjustable by external
capacitive load on FBK input
•
Multiple configurations, see Available PI6C2308
Configurations table
•
Input to output delay, less than 200ps
•
Multiple low skew outputs
- Output-output skew less than 200ps
- Device-device skew less than 600ps
- Two banks of four outputs, Hi-Z by two select inputs
•
Low Jitter, less than 200ps
•
3.3V operation
•
Space-saving Packages:
16-pin, 150-mil SOIC package (W16) (-1, -1H, -2, -3, -4, -6)
16-pin TSSOP package (L16) (-1, -1H)
•
Available in industrial and commercial temperatures
Functional Description
Providing two banks of four outputs, the PI6C2308 is a 3.3V zero-
delay buffer designed to distribute clock signals in applications
including PC, workstation, datacom, telecom, and high-performance
systems. Each bank of four outputs can be controlled by the select
inputs as shown in the Select Input Decoding Table.
The PI6C2308 provides 8 copies of a clock signal that has 200ps
phase error compared to a reference clock. The skew between the
output clock signals for PI6C2308 is less than 200ps. When there
are no rising edges on the REF input, the PI6C2308 enters a power
down state. In this mode, the PLL is off and all outputs are Hi-Z.
This results in less than 12µA of current draw. The Select Input
Decoding Table shows additional examples when the PLL shuts
down. The PI6C2308 configuration table shows all available devices.
The base part, PI6C2308-1, provides output clocks in sync with a
reference clock. With faster rise and fall times, the PI6C2308-1H
is the high drive version of the PI6C2308-1. Depending on which
output drives the feedback pin, PI6C2308-2 provides 2X and 1X
clock signals on each output bank. The PI6C2308-3 allows the user
to obtain 4X and 2X frequencies on the outputs. The PI6C2308-4
provides 2X clock signals on all outputs. PI6C2308 (-1, -2, -3, -4) allows
bank B to be Hi-Z when all output clocks are not required.The
PI6C2308-6 allows bank B to switch from Reference clock to half
of the frequency of Reference clock using the control inputs S1 and
S2 if Bank A is connected to feedback FBK. In addition, using the
control inputs S1 and S2, the PI6C2308-6 allows bank A to switch
from Reference clock to 2X the frequency of Reference clock if
Bank B is connected to feedback FBK. For testing purposes, the
select inputs connect the input clock directly to outputs.
Block Diagrams
÷2
REF
PLL
MUX
FBK
CLKA1
CLKA2
Extra Divider (-3, -4)
CLKA3
CLKA4
÷2
CLKB1
S2
S1
Select Input
Decoding
Extra Divider (-2,-3)
CLKB2
CLKB3
PI6C2308 (-1, -1H, -2, -3, -4)
CLKB4
REF
PLL
MUX
S2
S1
Select Input
Decoding
÷2
MUX
FBK
CLKA1
CLKA2
CLKA3
CLKA4
Pin Configuration PI6C2308 (1, 1H, 2, 3, 4, 6)
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
16-Pin
13
W, L
12
11
10
9
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
PI6C2308-6
CLKB1
CLKB2
CLKB3
CLKB4
1
PS8384D
06/26/01
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308
3.3V Zero Delay Buffer
Select Input Decoding for PI6C2308 (-1, -1H, -2, -3, -4)
S2
0
0
1
1
S1
0
1
0
1
CLKA [1-4]
Hi- Z
Driven
Driven
Driven
CLKB [1-4]
Hi- Z
Hi- Z
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
Y
N
Y
N
Select Input Decoding for PI6C2308-6
S2
0
0
1
1
S1
0
1
0
1
CLKA [1-4]
Hi- Z
Driven = Reference
Driven = PLL
Driven = PLL
CLKB [1-4]
Hi- Z
Driven = Reference/2
Driven = PLL
Driven = PLL/2
Output Source
PLL
Reference
PLL
PLL
PLL Shutdown
Y
Y
N
N
Available PI6C2308 Configurations
D e vice
PI6C2308- 1
PI6C2308- 1H
PI6C2308- 2
PI6C2308- 2
PI6C2308- 3
PI6C2308- 3
PI6C2308- 4
PI6C2308- 6
PI6C2308- 6
Fe e dback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A
Bank B
Bank A Fre que ncy
Reference
Reference
Reference
2X Reference
2X Reference
4X Reference
2X Reference
Reference
Reference or 2X Reference
Bank B Fre que ncy
Reference
Reference
Reference/2
Reference
Reference
2X Reference
2X Reference
Reference or Reference/2
Reference
2
PS8384D
06/26/01
REF - Input to CLKA/CLKB Delay (ps)
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308
3.3V Zero Delay Buffer
Zero Delay and Skew Control
REF. Input to CLKA/CLKB Delay vs. Difference in Loading between FBK pin and CLKA/CLKB pins
800
600
400
200
0
-25
-200
-20
-15
-10
-5
0
5
10
15
20
25
-400
PI6C2308-1H
-600
-800
PI6C2308-1,2,3,4,6
-900
-1000
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
To close the feedback loop of the PI6C2308, the FBK pin can be
driven from any of the 8 available output pins. The output driving
the FBK pin will be driving a total load of 7pF plus any additional load
that it drives. The relative loading of this output (with respect to the
remaining outputs) can adjust the input-output delay. This is shown
in the graph above.
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally loaded. If
input-output delay adjustments are required, use the above graph to
calculate loading differences between the feedback output and
remaining outputs.
Maximum Ratings
Supply Voltage to Ground Potential ...................0.5V to +7.0V
DC Input Voltage (Except REF) .................. 0.5V to V
DD
+0.5V
DC Input Voltage REF ................................................ 0.5 to 7V
Storage Temperature ........................................ 65ºC to +150ºC
Maximum Soldering Temperature (10 seconds) ................ 260ºC
Junction Temperature ....................................................... 150ºC
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .................................. >2000V
Operating Conditions
Parame te r
V
DD
T
A
C
L
C
IN
(Over operating range, T
A
= 0ºC to +70°C, V
CC
= 3.3V ±0.3V)
De s cription
Supply Voltage
Operating Temperature
(Ambient)
Load Capacitance
Input Capacitance
M in.
3.0
0
M ax.
3.6
70
30
7
Units
V
ºC
pF
3
PS8384D
06/26/01
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308
3.3V Zero Delay Buffer
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Signal
REF
(1)
C LK A1
(2)
C LK A2
(2)
V
DD
GN D
C LK B1
(2)
C LK B2
(2)
S2
(3)
S1
(3)
C LK B3
(2)
C LK B4
(2)
GN D
V
DD
C LK A3
(2)
C LK A4
(2)
FBK
C lock output, Bank A
C lock output, Bank A
3.3V supply
Ground
C lock output, Bank B
C lock output, Bank B
Select input, bit 2
Select input, bit 1
C lock output, Bank B
C lock output, Bank B
Ground
3.3V, supply
C lock output, Bank A
C lock output, Bank A
PLL feedback input
D e s cription
Input reference frequency, 5V tolerant input, allows spread spectrum clock input
Electrical Characteristics for Commercial Temperature Devices
Parame te r
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
(PD mode)
I
DD
I
DD
De s cription
Input LOW Voltage
(4)
Input HIGH Voltage
(4)
Input LOW Current
Input HIGH Current
Output LOW Voltage
(5)
Output HIGH Voltage
(5)
Power Down Supply Current
Supply Current
Supply Current
V
IN
= 0V
V
IN
= V
DD
I
OL
= 8mA (1, 2, 3,4, 6)
I
OL
= 12mA (- 1H)
I
OH
= 8mA (1, 2, 3,4, 6)
I
OH
= 12mA (- 1H)
REF = 0 MHz
Unloaded outputs, 66.66 MHz,
Select inputs at V
DD
or GND
Unloaded outputs 100 MHz Select
Inputs @ V
DD
or GND
Te s t Conditions
M in.
2.0
2.4
M ax.
0.8
50
100
0.4
V
12
39
54
mA
µA
Units
V
µA
4
PS8384D
06/26/01
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2308
3.3V Zero Delay Buffer
Switching Characteristics
(5)
for Commercial Temperature Device
Parame te rs
t
1
t
2
N ame
O utput Frequency
Duty C ycle
(5)
= t
2
÷
t
1
(2308- 1H)
Duty C ycle = t
2
÷
t
1
(2308- 1, - 2, - 3, - 4, - 6)
Rise Time
(4)
@30pF
t
3
Rise Time
(4)
@15pF
Rise Time
(4)
@30pF (1H)
Fall Time
(4)
@30pF
t
4
Fall Time
(4)
@15pF
Fall Time
(4)
@30pF (1H)
O utput to O utput Skew
(4)
on same
bank (23081,1H,2,3,4,6)
t
5
O utput Bank A to O utput Bank B
Skew
(4
) (23081,1H,4)
O utput Bank A to O utput Bank B
Skew
(4
) (23082,3,6)
t
6
(Phase
Error)
t
7
t
8
All outputs equally loaded, V
DD
/2
All outputs equally loaded, V
DD
/2
All outputs equally loaded, V
DD
/2
0
0
1
200
10 0
400
1. 0
ms
ps
Measured between 0.8V and 2.0V
Te s t Conditions
15pF to 30pF load
Measured at 1.4V, for high drive output
Measured at 1.4V, for normal drive output
M in.
10
45
40
50
50
Typ.
M ax. Units
134
55
60
2. 2
1. 5
1. 5
2. 2
1. 5
1. 2 5
200
200
400
± 200
600
V/ns
ps
ns
%
MHz
Input to O utput Delay, REF Rising Edge
Measured at V
DD
/2
to FBK Rising Edge
(4)
Device to Device Skew
(4)
O utput Slew
Rate
(4)
Measured at V
DD
/2 on the
FBK pins of devices
Measured between 0.8V and 2.0V on -
1H device using
Test C ircuit #2
Measured at 66.67 MHz,
loaded 30pF outputs
Measured at 133 MHz,
loaded 15pF outputs
Measured at 66.6 MHz,
loaded 30pF outputs
Stable power supply, valid clocks
presented on REF and FBK pins
t
J
C ycle- to- C ycle Jitter
(4)
(23081,1H,4)
C ycle- to- C ycle Jitter
(4)
(23082,3,6)
PLL Lock Time
(4)
t
J
t
LO CK
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. REF and FBK inputs have a threshhold voltage of V
DD
/2.
5. For definition of t
1-8
, see Switching Waveforms on page 8.
5
PS8384D
06/26/01
Power technology
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