DY6000
™
Family
FAST
Field Programmable Gate Array
™
Features
•
•
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•
•
•
Predictable, Fast, Patented Active Repeater™
Architecture
I/O Data-Transfer Rates up to 200MHz
2.7ns I/O Clock-to-Output Time with 10pf Load;
3.2ns with 50pf Load
1.4ns I/O Input Register Setup Time
9,000 to 55,000 Usable Gates
32-Bit Synchronous 8ns-Access, Two-Clock,
Two-Port SRAM in Every Logic Block, to
Support 125MHz FIFOs
Two PLLs for 8MHz-to-200MHz Clock
Multiplication, Division, and Locking with
Programmable Latency
Ten Clock Trees with 200ps Worst-Case Clock
Skew
150ps Worst-Case Pin-to-Pin Skew Between
Registered Logic Outputs to Support Fast Buses
In-System Reprogrammability
Dynamic Single-Block Reconfigurability
TTL, LV-TTL, GTL, and GTLP Interface Levels;
24mA IOL Drive for GTL, 48mA IOL Drive for
GTLP
Up to Nineteen LVDS-Compatible Input Pairs
Up to Nineteen Differential LV-PECL Input Pairs
66MHz, 64-Bit, Zero-Wait-State PCI Soft Core
3.3V Operation with 5V-Tolerant I/O
Hot-Swappability – no System Shutdown
Required When Exchanging Circuit Boards
JTAG (IEEE1149.1) Boundary-Scan
Conformance
Individual Slew-Rate Controls for Each Output
Fully-Automatic Design Implementation Using
DynaTool™
432-Pin EBGA and 240-Pin EQFP Packages
•
•
•
•
•
•
Applications Examples
•
Data Communications: Gigabit Ethernet, ATM,
Fibre Channel, Token Ring, SONET – Switching,
Routing, CRC Functions
Telecommunications
High-Speed Graphics
On-the-Fly-Reconfigurable Systems
Servers and Supercomputers
PCI Interfaces
ASIC Emulation
Semiconductor Testers
High-Performance Instrumentation
Medical Imaging Systems
•
•
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•
•
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•
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•
•
•
Device
DY6009
DY6020
DY6035
DY6055
Gates
9,000
20,000
35,000
55,000
Logic
Blocks
256
576
1,024
1,600
Max User
SRAM Bits
8,192
18,432
32,768
51,200
Flip- flops
768
1,536
2,560
3,840
Clock
Trees
10
10
10
10
I/O Blocks
128
192
256
320
Table 1: DY6000 Family
DY6000 Family Datasheet Revision 1.1
April 1999
DY6000 - Fast Field Programmable Gate Array
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DY6000 Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Performance Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
High-Performance Active Repeater Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Top-Level Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Routing Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Input/Output Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
External GTL/GTLP and LV-PECL Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Logic Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Phase-Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Advance Estimates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Configuration Pin Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reconfiguration and Resetting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Configuration-Related Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Product Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Clock and Set/Reset Buffer Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
I/O Block Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Logic Block Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
432-Pin EBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
240-Pin EQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
432-Pin EBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
240-Pin Thermal Enhanced EQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Sales and Corporate Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Back 3 Pages
Page 2
DY6000 Family Datasheet Revision 1.1
DY6000 - Fast Field Programmable Gate Array
Introduction
DynaChip’s third generation DY6000 family of Fast Field Programmable Gate Array devices
incorporate improvements in internal architecture and in I/O versatility. Fabricated using a
deep-submicron CMOS process, this family of devices supports applications with system
clock and I/O rates up to 200MHz – well above the rates achievable using conventional
FPGAs.
All DY6000 family devices feature DynaChip’s patented Active Repeater™ architecture,
which provides shorter, highly-predictable internal routing path delays. Every I/O pin can be
programmed to LV-TTL or GTL/GTLP interface levels as well as to standard-TTL and
CMOS levels to support the fast data rates of high-performance applications.
Every logic block in DY6000 family devices contains 32 bits of synchronous two-clock two-
port SRAM, with 8ns access time; an architecture particularly well suited to implementing
many small, fast, distributed SRAMs or FIFOs in customer designs. In data rate matching
applications, the FIFO can have completely independent read and write clocks.
High operating frequencies, on-chip distributed SRAM/FIFO, fast I/O, and PCI
compatibility make DY6000 family devices ideal for high-performance data
communications, telecommunications, graphics, and emulation applications.
The SRAM-based DY6000 family devices enable in-circuit configuration and
reprogramming on-the-fly. Dynamic single-block reconfiguration is also possible, where a
portion of the device may be reprogrammed without affecting the operation of the remaining
logic. DY6000 family devices are hot-swappable, so system operation remains uninterrupted
during power down for things like exchanging a circuit board.
DY6000 Family Datasheet Revision 1.1
Page 3
DY6000 - Fast Field Programmable Gate Array
DY6000 Enhancements
The DY6000 family incorporates numerous improvements:
• Wider functions in a single-logic level:
• 8:1 Mux
• 7-Input XOR
• 2-Bit Full Adder
• 2-Bit Identity Comparator
• 9-Input AND Gate
• 16-Input AND/OR Function
• Local Fast-Carry-Chain Paths:
• Higher-Performance Full Adders
• Higher-Performance Identity Comparators
• Higher-Performance Parity and CRC Logic
• 125MHz Distributed Two-Clock Data-Rate-Matching FIFOs:
• 32-Bit Two-Clock, Two-Port SRAM in Every Logic Block
• Separate Write Clock and Read Clocks
• External Reference Voltage for I/O Blocks
• Supports GTL and GTLP
• Higher-Current Drive:
• 48mA I
OL
in GTLP Mode (or 24mA I
OL
in GTL Mode)
• Programmable PLL Latency:
• Adjustable from -3.0ns to + 2.0ns in 150ps increments
• 19 LV-PECL/LVDS Differential Input Pairs
• Chip Power-Down Mode for ‘Green Design’
Page 4
DY6000 Family Datasheet Revision 1.1
DY6000 - Fast Field Programmable Gate Array
Performance Examples
All DY6000 family devices use DynaChip’s patented Active Repeater™ architecture to
support high-performance applications at clock rates and chip-to-chip data-transfer rates up
to 200MHz. Active repeaters significantly reduce routing delays even for routing-intensive
designs with high-fanout nets.
Table 2 gives the performance values of various macros implemented within a DY6055G
(fastest speed grade) device over commercial voltage and temperature ranges.
Circuit
Fully-Synchronous Loadable Up-Counters:
8-bit
16-bit
32-bit
64-bit
Adders:
8-Bit, Using Carry Chain
16-Bit, Using Carry Chain
4x4 Pipelined Multiplier
SRAM-Based FIFOs:
32x32
64-Bit Shift Register
125MHz
160MHz
47
64
7.5ns
8.8ns
145MHz
5
9
49
145MHz
140MHz
125MHz
100MHz
9
20
42
86
DY6055G
Logic Block Count
Table 2: Performance of Various Applications (Includes Routing Delays)
Assumptions: -G speed grade over commercial voltage and temperature range; 10pF load and fast slew-
rate setting on outputs.
Notes: When measuring these performance values over industrial voltage and tempera-
ture ranges, derate the values by 5 percent.
When comparing DY6000 family FPGA performance with competing products, all values in
Table 2 include all block routing delays within the same routing region.
The maximum chip-to-chip data-transfer rate is 250MHz assuming 10pF loads, GTL/GTLP
interface levels, and the fastest slew rate.
DY6000 Family Datasheet Revision 1.1
Page 5
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