DISCRETE SEMICONDUCTORS
DATA SHEET
PHN103
N-channel enhancement mode
MOS transistor
Product specification
Supersedes data of 1996 Nov 12
File under Discrete Semiconductors, SC13b
1997 Jun 20
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
FEATURES
•
High-speed switching
•
No secondary breakdown
•
Very low on-state resistance.
APPLICATIONS
•
Motor and actuator driver
•
Power management
•
Synchronized rectification.
DESCRIPTION
N-channel enhancement mode MOS transistor in an 8-pin
plastic SOT96-1 (SO8) package.
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
1
4
n.c. s
handbook, halfpage
PHN103
PINNING - SOT96-1 (SO8)
PIN
1
2
3
4
5
6
7
8
SYMBOL
n.c
s
s
g
d
d
d
d
source
source
gate
drain
drain
drain
drain
DESCRIPTION
not connected
d
5
d d d
8
MAM116
s
g
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
V
SD
V
GS
V
GSth
I
D
R
DSon
P
tot
PARAMETER
drain-source voltage (DC)
source-drain diode forward voltage
gate-source voltage (DC)
gate-source threshold voltage
drain current (DC)
drain-source on-state resistance
total power dissipation
I
D
= 1 mA; V
DS
= V
GS
T
s
= 80
°C
I
D
= 5.5 A; V
GS
= 10 V
T
s
= 80
°C
I
S
= 1.25 A
CONDITIONS
−
−
−
1
−
−
−
MIN.
1
±20
2.8
8.5
0.03
4
MAX.
30
V
V
V
V
A
Ω
W
UNIT
1997 Jun 20
2
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
V
GS
I
D
I
DM
P
tot
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
T
s
= 80
°C;
note 1
note 2
T
s
= 80
°C
T
amb
= 25
°C;
note 3
T
amb
= 25
°C;
note 4
T
stg
T
j
I
S
I
SM
Notes
1. T
s
is the temperature at the soldering point of the drain lead.
2. Pulse width and duty cycle limited by maximum junction temperature.
3. Device mounted on printed-circuit board with an R
th a-tp
(ambient to tie-point) of 27.5 K/W.
4. Device mounted on printed-circuit board with an R
th a-tp
(ambient to tie-point) of 90 K/W.
THERMAL CHARACTERISTICS
SYMBOL
R
th j-s
PARAMETER
thermal resistance from junction to soldering point
VALUE
17.5
storage temperature
operating junction temperature
T
s
= 80
°C
note 2
CONDITIONS
−
−
−
−
−
−
−
−65
−65
−
−
MIN.
PHN103
MAX.
30
±20
8.5
35
4
2.7
1.15
+150
+150
V
V
A
A
W
W
W
UNIT
°C
°C
Source-drain diode
source current (DC)
peak pulsed source current
5
20
A
A
UNIT
K/W
1997 Jun 20
3
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
PHN103
handbook, halfpage
8
MGG329
10
2
handbook, halfpage
ID
(A)
MGG330
Ptot
(W)
6
tp =
10
(1)
10
µs
100
µs
1 ms
tp
T
100 ms
tp
t
T
1
10
DC
VDS (V)
10
2
10 ms
4
P
1
δ
=
2
0
0
50
100
Ts (°C)
150
10
−1 −1
10
δ
= 0.01; T
s
= 80
°C.
(1) R
DSon
limitation.
Fig.2 Power derating curve.
Fig.3 SOAR.
1997 Jun 20
4
Philips Semiconductors
Product specification
N-channel enhancement mode
MOS transistor
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
C
iss
C
oss
C
rss
Q
G
Q
GS
Q
GD
t
d(on)
t
r
t
on
t
d(off)
t
f
t
off
PARAMETER
drain-source breakdown voltage
gate-source threshold voltage
drain-source leakage current
gate leakage current
drain-source on-state resistance
input capacitance
output capacitance
reverse transfer capacitance
total gate charge
gate-source charge
gate-drain charge
CONDITIONS
V
GS
= 0; I
D
= 10
µA
V
GS
= V
DS
; I
D
= 1 mA
V
GS
= 0; V
DS
= 24 V
V
GS
=
±20
V; V
DS
= 0
V
GS
= 4.5 V; I
D
= 2.75 A
V
GS
= 10 V; I
D
= 5.5 A
V
GS
= 0; V
DS
= 24 V; f = 1 MHz
V
GS
= 0; V
DS
= 24 V; f = 1 MHz
V
GS
= 0; V
DS
= 24 V; f = 1 MHz
V
GS
= 10 V; V
DD
= 15 V; I
D
= 4 A
V
GS
= 10 V; V
DD
= 15 V; I
D
= 4 A
V
GS
= 10 V; V
DD
= 15 V; I
D
= 4 A
V
GS
= 0 to 10 V; V
DD
= 15 V;
I
D
= 1 A; R
L
= 15
Ω;
R
gen
= 6
Ω
V
GS
= 0 to 10 V; V
DD
= 15 V;
I
D
= 1 A; R
L
= 15
Ω;
R
gen
= 6
Ω
V
GS
= 0 to 10 V; V
DD
= 15 V;
I
D
= 1 A; R
L
= 15
Ω;
R
gen
= 6
Ω
V
GS
= 10 to 0 V; V
DD
= 15 V;
I
D
= 1 A; R
L
= 15
Ω;
R
gen
= 6
Ω
V
GS
= 10 to 0 V; V
DD
= 15 V;
I
D
= 1 A; R
L
= 15
Ω;
R
gen
= 6
Ω
V
GS
= 10 to 0 V; V
DD
= 15 V;
I
D
= 1 A; R
L
= 15
Ω;
R
gen
= 6
Ω
V
GD
= 0; I
S
= 1.25 A
I
S
= 1.25 A; di/dt = 100 A/µs
MIN.
30
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
TYP.
−
−
−
−
−
−
750
520
200
25
3
7.5
PHN103
MAX.
−
2.8
100
±100
0.05
0.03
−
−
−
40
−
−
−
−
35
−
−
150
UNIT
V
V
nA
nA
Ω
Ω
pF
pF
pF
nC
nC
nC
Switching times
(see Fig.4)
turn-on delay time
rise time
turn-on switching time
turn-off delay time
fall time
turn-off switching time
7
10
17
35
40
75
ns
ns
ns
ns
ns
ns
Source-drain diode
V
SD
t
rr
source-drain diode forward
voltage
reverse recovery time
−
−
−
70
1
−
V
ns
1997 Jun 20
5
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