Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general
purpose
switching
applications.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
200
5.0
60
0.9
UNIT
V
A
W
Ω
PINNING - SOT428
PIN
1
2
3
tab
gate
drain
source
DESCRIPTION
PIN CONFIGURATION
tab
SYMBOL
d
g
2
drain
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
I
D
I
DM
P
D
∆P
D
/∆T
mb
V
GS
E
AS
I
AS
T
j
, T
stg
Continuous drain current
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Single pulse avalanche
energy
Peak avalanche current
Operating junction and
storage temperature range
CONDITIONS
T
mb
= 25 ˚C; V
GS
= 10 V
T
mb
= 100 ˚C; V
GS
= 10 V
T
mb
= 25 ˚C
T
mb
= 25 ˚C
T
mb
> 25 ˚C
V
DD
≤
50 V; starting T
j
= 25˚C; R
GS
= 50
Ω;
V
GS
= 10 V
V
DD
≤
50 V; starting T
j
= 25˚C; R
GS
= 50
Ω;
V
GS
= 10 V
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
5
3.5
20
60
0.4
±
30
40
5
175
UNIT
A
A
A
W
W/K
V
mJ
A
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
TYP.
-
pcb mounted, minimum
footprint
50
MAX.
2.5
-
UNIT
K/W
K/W
October 1997
1
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
ELECTRICAL CHARACTERISTICS
T
j
= 25 ˚C unless otherwise specified
SYMBOL
V
(BR)DSS
∆V
(BR)DSS
/
∆T
j
R
DS(ON)
V
GS(TO)
g
fs
I
DSS
I
GSS
Q
g(tot)
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
d
L
s
C
iss
C
oss
C
rss
PARAMETER
Drain-source breakdown
voltage
Drain-source breakdown
voltage temperature coefficient
Drain-source on resistance
Gate threshold voltage
Forward transconductance
Drain-source leakage current
Gate-source leakage current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA
V
DS
= V
GS
; I
D
= 0.25 mA
V
GS
= 10 V; I
D
= 2.5 A
V
DS
= V
GS
; I
D
= 0.25 mA
V
DS
= 50 V; I
D
= 2.5 A
V
DS
= 200 V; V
GS
= 0 V
V
DS
= 160 V; V
GS
= 0 V; T
j
= 150 ˚C
V
GS
=
±30
V; V
DS
= 0 V
I
D
= 4.8 A; V
DD
= 160 V; V
GS
= 10 V
MIN.
200
-
-
2.0
1.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP.
-
0.25
0.68
3.0
3.5
0.1
1
10
11
2
5.3
7
29
27
22
3.5
7.5
300
60
20
MAX.
-
-
0.9
4.0
-
25
250
100
15
3
7
-
-
-
-
-
-
-
-
-
UNIT
V
V/K
Ω
V
S
µA
µA
nA
nC
nC
nC
ns
ns
ns
ns
nH
nH
pF
pF
pF
V
DD
= 100 V; I
D
= 4.8 A;
R
G
= 18
Ω;
R
D
= 20
Ω
Measured from tab to centre of die
Measured from source lead solder
point to source bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
T
j
= 25 ˚C unless otherwise specified
SYMBOL
I
S
I
SM
V
SD
t
rr
Q
rr
PARAMETER
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
T
mb
= 25˚C
T
mb
= 25˚C
I
S
= 5.2 A; V
GS
= 0 V
I
S
= 4.8 A; V
GS
= 0 V;
dI/dt = 100 A/µs
MIN.
-
-
-
-
-
TYP.
-
-
-
114
0.8
MAX.
5
20
1.5
-
-
UNIT
A
A
V
ns
µC
October 1997
2
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
1E+01
Zth j-mb / (K/W)
BUKX52
1E+00
0.5
0.2
0.1
0.05
1E-01 0.02
0
0
20
40
60
80 100
Tmb / C
120
140
160
180
P
D
t
p
D=
t
p
T
t
1E-02
1E-07
T
1E-05
1E-03
t/s
1E-01
1E+01
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
ID%
Normalised Current Derating
10
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
120
110
100
90
80
70
60
50
40
30
20
10
0
ID, Drain current (Amps)
10 V
7V
Tj = 25 C
PHP5N20
6V
8
5.5 V
6
5V
4
VGS = 4.5 V
2
0
20
40
60
80 100
Tmb / C
120
140
160
180
0
0
5
10
15
20
VDS, Drain-Source voltage (Volts)
25
30
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
10 V
ID, Drain current (Amps)
PHP5N20E
Fig.5. Typical output characteristics.
I
D
= f(V
DS
); parameter V
GS
RDS(on), Drain-Source on resistance (Ohms)
4.5 V
5V
5.5 V
100
3
2.5
PHP5N20
6V
7V
10
R
DS
N)
(O
=V
/
DS
ID
tp = 10 us
100 us
1 ms
2
1.5
VGS = 10 V
1
0.5
Tj = 25 C
0
1
DC
10 ms
100 ms
0.1
1
10
100
VDS, Drain-source voltage (Volts)
1000
0
2
4
6
ID, Drain current (Amps)
8
10
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance.
R
DS(ON)
= f(I
D
); parameter V
GS
October 1997
3
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
12
10
ID, Drain current (Amps)
VDS = 30 V
PHP5N20E
Tj = 25 C
4
VGS(TO) / V
max.
typ.
8
6
4
3
Tj = 175 C
min.
2
1
2
0
0
0
2
4
6
VGS, Gate-source voltage (Volts)
8
10
-60
-20
20
60
Tj / C
100
140
180
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
); parameter T
j
gfs, Transconductance (S)
VDD = 30 V
4
Tj = 25 C
3
Tj = 175 C
2
PHP5N20E
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 0.25 mA; V
DS
= V
GS
ID / A
SUB-THRESHOLD CONDUCTION
5
1E-01
1E-02
1E-03
2%
typ
98 %
1E-04
1
1E-05
0
1E-06
0
2
4
6
8
ID, Drain current (Amps)
10
12
0
1
2
VGS / V
3
4
Fig.8. Typical transconductance.
g
fs
= f(I
D
); parameter T
j
a
Normalised RDS(ON) = f(Tj)
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Ciss, Coss, Crss, Junction capacitances (pF) PHP5N20E
Ciss
Coss
Crss
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1000
100
10
-60
-20
20
60
Tj / C
100
140
180
1
1
10
100
VDS, Drain-source voltage (Volts)
1000
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 2.5 A; V
GS
= 10 V
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
October 1997
4
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
15
VGS, Gate-Source voltage (Volts)
ID = 4.8 A
Tj = 25 C
VDS = 40 V
100 V
PHP5N20E
160 V
20
IF, Source-drain diode current (Amps)
VGS = 0 V
PHP5N20E
15
10
Tj = 175 C
10
5
Tj = 25 C
5
0
0
5
10
Qg, Gate charge (nC)
15
20
0
0
0.5
1
VSDS, Source-drain voltage (Volts)
1.5
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Switching times (ns)
PHP5N20E
Fig.16. Source-Drain diode characteristic.
I
F
= f(V
SDS
); parameter T
j
EAS, Normalised unclamped inductive energy (%)
100
tr
td(off)
tf
10
td(on)
VDD = 100 V
VGS = 10 V
RD = 20 Ohms
ID = 4.8 A
Tj = 25 C
20
40
60
RG, Gate resistance (Ohms)
80
100
120
110
100
90
80
70
60
50
40
30
20
10
0
1
0
20
40
60
80
Starting Tj ( C)
100
120
140
160
180
Fig.14. Typical switching times.
t
d(on)
, t
r
, t
d(off)
, t
f
= f(R
G
)
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
Fig.17. Normalised unclamped inductive energy.
E
AS
% = f(T
j
)
1.15
1.1
1.05
1
0.95
0.9
+
L
VDS
VGS
0
RGS
T.U.T.
R 01
shunt
VDD
-
-ID/100
0.85
-100
-50
0
50
Tj, Junction temperature (C)
100
150
Fig.15. Normalised drain-source breakdown voltage.
V
(BR)DSS
/V
(BR)DSS 25 ˚C
= f(T
j
)
Fig.18. Unclamped inductive test circuit.
2
E
AS
=
0.5
⋅
LI
D
⋅
V
(BR)DSS
/(V
(BR)DSS
−
V
DD
)
October 1997
5
Rev 1.100
Medical Electronics
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