• Phase-locked loop clock distribution for Double Data
Rate Synchronous DRAM applications
• Distributes one clock input to six differential outputs
• External feedback pin FBIN is used to synchronize the
outputs to the clock input
• Conforms to the DDR1 specification
• Spread Aware™ for EMI reduction
• 28-pin SSOP package
Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD
operation and differential output levels.
This device is a zero delay buffer that distributes a clock input
CLKIN to six differential pairs of clock outputs (CLKT[0:5],
CLKC[0:5]) and one feedback clock output FBOUT. The clock
outputs are controlled by the input clock CLKIN and the
feedback clock FBIN.
The two line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clock CLKIN and the
feedback clock FBIN to provide high-performance, low-skew,
low–jitter output differential clocks.
Block Diagram
Pin Configuration
10
SCLK
SDATA
Serial
Interface
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKIN
NC
AVDD
AGND
VDD
CLKT2
CLKC2
CY28358
CLKT0
CLKC0
CLKT1
CLKC1
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLKIN
PLL
FBIN
CLKT4
CLKC4
CLKT5
CLKC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
NC
FBIN
FBOUT
NC
CLKT3
CLKC3
GND
AVDD
FBOUT
28 pin SSOP
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 10
www.SpectraLinear.com
CY28358
Pin Description
[1]
Pin
8
20
2,4,13,17,24,26
1,5,14,16,25,27
19
Name
CLKIN
FBIN
CLKT(0:5)
CLKC(0:5)
FBOUT
I/O
I
I
O
O
O
Clock Input.
Description
Input
Feedback Clock Input.
Connect to FBOUT for Input
accessing the PLL.
Clock Outputs
Clock Outputs
Feedback Clock Output.
Connect to FBIN for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
Output
Differential Outputs
Electrical Characteristics
7
22
SCLK
SDATA
I
I/O
Serial Clock Input.
Clocks data at SDATA into Data Input for the two line serial bus
the internal register.
Serial Data Input.
Input data is clocked to the
internal register to enable/disable individual
outputs. This provides flexibility in power
management.
2.5V Power Supply for Logic
2.5V Power Supply for PLL
Ground
Analog Ground for PLL
Not Connected
Data Input and Output for the two line
serial bus
3,12,23
10
6,15,28
11
9, 18, 21
VDD
AVDD
GND
AGND
NC
2.5V Nominal
2.5V Nominal
Function Table
Inputs
VDDA
GND
GND
2.5V
2.5V
2.5V
CLKIN
L
H
L
H
< 20 MHz
CLKT(0:5)
[2]
L
H
L
H
Hi-Z
Outputs
CLKC(0:5)
[2]
H
L
H
L
Hi-Z
FBOUT
L
H
L
H
Hi-Z
PLL
BYPASSED/OFF
BYPASSED/OFF
On
On
Off
Zero Delay Buffer
When used as a zero delay buffer the CY28358 will likely be
in a nested clock tree application. For these applications the
CY28358 offers a clock input as a PLL reference. The
CY28358 then can lock onto the reference and translate with
near zero delay to low-skew outputs. For normal operation, the
external feedback input, FBIN, is connected to the feedback
output, FBOUT. By connecting the feedback output to the
feedback input the propagation delay through the device is
eliminated. The PLL works to align the output edge with the
input reference edge thus producing a near zero delay. The
reference frequency affects the static phase offset of the PLL
and thus the relative delay between the inputs and outputs.
When VDDA is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Power Management
The individual output enable/disable control of the CY28358
allows the user to implement unique power management
schemes into the design. Outputs are three-stated when
disabled through the two-line interface as individual bits are
set low in Byte0 and Byte1 registers. The feedback output
FBOUT cannot be disabled via two line serial bus. The
enabling and disabling of individual outputs is done in such a
manner as to eliminate the possibility of partial “runt” clocks.
Notes:
1. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high
frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two line serial interface.
Rev 1.0, November 20, 2006
Page 2 of 10
CY28358
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
T
Data Protocol
The clock driver serial protocol accepts block write, and block
read operations from the controller. For block write/read
operation, the bytes must be accessed in sequential order
from lowest to highest byte (most significant bit first) with the
ability to stop after any complete byte has been transferred.
The block write and block read protocol is outlined in
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