ICs for Communications
Extended PCM Interface Controller
EPIC
®
-1
PEB 2055 / PEF 2055
EPIC
®
-S
PEB 2054 / PEF 2054
User’s Manual 02.97
Versions A3
Versions 1.0
PEB 2055
PEF 2055
Revision History:
Previous Release:
Page (in
Previous
Release)
Page
(in User’s
Manual)
User’s Manual 02.97
Technical Manual 02.92 (Editorial Update)
Subjects (major changes since last revision)
Edition 02.97
This edition was realized using the software system FrameMaker
®
.
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
©
Siemens AG 7/23/97.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we
will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-
curred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components
1
of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems
2
with the express
written approval of the Semiconductor Group of Siemens AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-
man life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PEB 2055
PEF 2055
Table of Contents
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.7.1
1.7.1.1
1.7.1.2
1.7.1.3
1.7.1.4
1.7.2
1.7.3
2
2.1
2.2
2.3
2.4
2.5
2.6
3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.5.1
3.5.2
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4
3.5.3
Page
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Using the EPIC-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
System Integration and Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Digital Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Switching, Layer-1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Decentralized D-Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Central D-Channel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Mixed D-Channel Processing, Signaling Decentralized,
Packet Data Centralized
21
Analog Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Packet Handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Configurable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Memory Structure and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Pre-processed Channels, Layer-1 Support . . . . . . . . . . . . . . . . . . . . . . . . . .31
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Operational Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Microprocessor Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
EPIC
®
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PCM-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Configurable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Switching Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
EPIC
®
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Control Memory Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Initialization of Pre-processed Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Initialization of the Upstream Data Memory (DM) Tristate Field . . . . . . . . . .45
Activation of the PCM and CFI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Semiconductor Group
3
02.97
PEB 2055
PEF 2055
Table of Contents
4
4.1
4.2
4.2.1
4.2.1.1
4.2.1.2
4.2.1.3
4.2.1.4
4.2.1.5
4.2.1.6
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.2.4
4.2.2.5
4.2.2.6
4.2.3
4.2.3.1
4.2.3.2
4.2.3.3
4.2.4
4.2.4.1
4.2.4.2
4.2.4.3
4.2.4.4
4.2.4.5
4.2.4.6
4.2.4.7
4.2.5
4.2.5.1
4.2.5.2
4.2.5.3
4.2.6
4.2.6.1
4.2.6.2
4.2.6.3
4.2.6.4
4.2.6.5
4.2.6.6
4.2.6.7
Page
Detailed Register Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Register Address Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
PCM Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
PCM-Mode Register (PMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Bit Number per PCM-Frame (PBNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
PCM-Offset Downstream Register (POFD) . . . . . . . . . . . . . . . . . . . . . . . . . .50
PCM-Offset Upstream Register (POFU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
PCM-Clock Shift Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
PCM-Input Comparison Mismatch (PICM) . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Configurable Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Configurable Interface Mode Register 1 (CMD1) . . . . . . . . . . . . . . . . . . . . . .53
Configurable Interface Mode Register 2 (CMD2) . . . . . . . . . . . . . . . . . . . . . .55
Configurable Interface Bit Number Register (CBNR) . . . . . . . . . . . . . . . . . . .58
Configurable Interface Time Slot Adjustment Register (CTAR) . . . . . . . . . . .58
Configurable Interface Bit Shift Register (CBSR) . . . . . . . . . . . . . . . . . . . . . .59
Configurable Interface Subchannel Register (CSCR) . . . . . . . . . . . . . . . . . .60
Memory Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Memory Access Control Register (MACR) . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Memory Access Address Register (MAAR) . . . . . . . . . . . . . . . . . . . . . . . . . .65
Memory Access Data Register (MADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Synchronous Transfer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Synchronous Transfer Data Register (STDA) . . . . . . . . . . . . . . . . . . . . . . . .67
Synchronous Transfer Data Register B (STDB) . . . . . . . . . . . . . . . . . . . . . .67
Synchronous Transfer Receive Address Register A (SARA) . . . . . . . . . . . . .68
Synchronous Transfer Receive Address Register B (SARB) . . . . . . . . . . . . .69
Synchronous Transfer Transmit Address Register A (SAXA) . . . . . . . . . . . .69
Synchronous Transfer Transmit Address Register B (SAXB) . . . . . . . . . . . .70
Synchronous Transfer Control Register (STCR) . . . . . . . . . . . . . . . . . . . . . .70
Monitor/Feature Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
MF-Channel Active Indication Register (MFAIR) . . . . . . . . . . . . . . . . . . . . . .71
MF-Channel Subscriber Address Register (MFSAR) . . . . . . . . . . . . . . . . . . .72
Monitor/Feature Control Channel FIFO (MFFIFO) . . . . . . . . . . . . . . . . . . . . .73
Status/Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Signaling FIFO (CIFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Timer Register (TIMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Interrupt Status Register (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Operation Mode Register (OMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Semiconductor Group
4
02.97
PEB 2055
PEF 2055
Table of Contents
Page
4.2.6.8 Version Number Status Register (VNSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5
5.1
5.1.1
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.1.3
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
5.3
5.3.1
5.3.2
5.3.3
5.3.3.1
5.3.3.2
5.3.3.3
5.3.3.4
5.4
5.4.1
5.4.2
5.4.3
5.4.3.1
5.4.3.2
5.4.4
5.4.4.1
5.4.4.2
5.4.4.3
5.5
5.5.1
5.5.2
5.5.2.1
5.5.2.2
5.5.2.3
5.5.3
5.5.3.1
5.5.3.2
5.6
Application Hints
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
IOM
®
and SLD Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Configuration of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
PCM Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
PCM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
PCM Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
PCM Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Configurable Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CFI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CFI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
CFI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Data and Control Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Memory Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Indirect Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Memory Access Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Access to the Data Memory Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Access to the Data Memory Code (Tristate) Field . . . . . . . . . . . . . . . . . . . .139
Access to the Control Memory Data Field . . . . . . . . . . . . . . . . . . . . . . . . . .142
Access to the Control Memory Code Field . . . . . . . . . . . . . . . . . . . . . . . . . .144
Switched Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
CFI - PCM Time Slot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Subchannel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
CFI - CFI Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
PCM - PCM Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Switching Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Internal Procedures at the Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . .167
How to Determine the Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Example: Switching of Wide Band ISDN Channels with the EPIC
®
. . . . . . .172
Preprocessed Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Initialization of Preprocessed Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Control/Signaling (CS) Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
Registers used in Conjunction with the CS Handler . . . . . . . . . . . . . . . . . .188
Access to Downstream C/I and SIG Channels . . . . . . . . . . . . . . . . . . . . . .190
Access to the Upstream C/I and SIG Channels . . . . . . . . . . . . . . . . . . . . . .191
Monitor/Feature Control (MF) Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Registers used in Conjunction with the MF Handler . . . . . . . . . . . . . . . . . .195
Description of the MF Channel Commands . . . . . . . . . . . . . . . . . . . . . . . . .200
µP
Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
5
02.97
Semiconductor Group
NXP MCU
京公网安备 11010802033920号
EEWORLD
