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NSBA143EDXV6T1

Description
trans prebias dual pnp sot563
CategoryDiscrete semiconductor    The transistor   
File Size133KB,12 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Environmental Compliance
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NSBA143EDXV6T1 Overview

trans prebias dual pnp sot563

NSBA143EDXV6T1 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerON Semiconductor
package instructionPLASTIC, CASE 463A-01, 6 PIN
Contacts6
Manufacturer packaging codeCASE 463A-01
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
Other featuresBUILT IN BIAS RESISTOR RATIO IS 1
Maximum collector current (IC)0.1 A
Collector-emitter maximum voltage50 V
ConfigurationSEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
Minimum DC current gain (hFE)15
JESD-30 codeR-PDSO-F6
JESD-609 codee3
Humidity sensitivity level1
Number of components2
Number of terminals6
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
Polarity/channel typePNP
Maximum power dissipation(Abs)0.5 W
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin (Sn)
Terminal formFLAT
Terminal locationDUAL
Maximum time at peak reflow temperature40
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
NSBA114EDXV6T1,
NSBA114EDXV6T5
Preferred Devices
Dual Bias Resistor
Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSBA114EDXV6T1
series, two BRT devices are housed in the SOT−563 package which is
ideal for low−power surface mount applications where board space is
at a premium.
(3)
R
1
Q
1
Q
2
R
2
(4)
R
1
(5)
(6)
http://onsemi.com
(2)
R
2
(1)
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
Available in 8 mm, 7 inch Tape and Reel
Lead Free Solder Plating
6
54
23
1
SOT−563
CASE 463A
PLASTIC
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted, common for Q
1
and Q
2
)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
−50
−50
−100
Unit
Vdc
Vdc
mAdc
xx = Specific Device Code
(see table on page 2)
D = Date Code
Symbol
P
D
Max
357
(Note 1)
2.9
(Note 1)
350
(Note 1)
Max
500
(Note 1)
4.0
(Note 1)
250
(Note 1)
−55 to
+150
Unit
mW
mW/°C
°C/W
NSBA114EDXV6T5 SOT−563
Unit
mW
xx D
MARKING DIAGRAM
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation
Derate above 25°C
Thermal Resistance Junction-to-Ambient
Characteristic
(Both Junctions Heated)
Total Device Dissipation
Derate above 25°C
Thermal Resistance Junction-to-Ambient
Junction and Storage
Temperature Range
1. FR−4 @ Minimum Pad
R
qJA
T
J
, T
stg
T
A
= 25°C
R
qJA
T
A
= 25°C
ORDERING INFORMATION
Device
Package
Shipping
4 mm pitch
4000/Tape & Reel
2 mm pitch
8000/Tape & Reel
NSBA114EDXV6T1 SOT−563
Symbol
P
D
DEVICE MARKING INFORMATION
mW/°C
°C/W
°C
See specific marking information in the device marking table
on page 2 of this data sheet.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2004
1
January, 2004 − Rev. 3
Publication Order Number:
NSBA114EDXV6/D
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