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5962R9563701VXC

Description
HCT SERIES, QUAD 2-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14
Categorylogic    logic   
File Size410KB,8 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
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5962R9563701VXC Overview

HCT SERIES, QUAD 2-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14

5962R9563701VXC Parametric

Parameter NameAttribute value
Parts packaging codeDFP
package instructionDFP, FL14,.3
Contacts14
Reach Compliance Codeunknown
Other featuresRADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHONOLOGY
seriesHCT
JESD-30 codeR-CDFP-F14
JESD-609 codee4
length9.525 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.004 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Encapsulate equivalent codeFL14,.3
Package shapeRECTANGULAR
Package formFLATPACK
power supply5 V
Prop。Delay @ Nom-Sup22 ns
propagation delay (tpd)20 ns
Certification statusNot Qualified
Schmitt triggerNO
Filter level38535V;38534K;883S
Maximum seat height2.92 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceGOLD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
total dose100k Rad(Si) V
width6.285 mm
Base Number Matches1
TM
HCTS00MS
Radiation Hardened Quad
2-Input NAND Gate
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
August 1995
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
• Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
• Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
• Cosmic Ray Upset Immunity < 2 x 10
-9
Errors/Gate Day (Typ)
• Latch-Up Free Under Any Conditions
• Military Temperature Range:
-55
o
C
to
+125
o
C
GND 7
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• CMOS Input Compatibility Ii
5µA at VOL, VOH
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14
TOP VIEW
A1
B1
Y1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
B4
A4
Y4
B3
A3
Y3
Description
The Intersil HCTS00MS is a Radiation Hardened Quad 2-Input
NAND Gate. A high on both inputs forces the output to a Low state.
The HCTS00MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS00MS is supplied in a 14 lead Ceramic flatpack
(K suf fix) or a SBDIP Package (D suffix).
A2
B2
Y2
GND
TRUTH TABLE
INPUTS
An
L
Bn
L
H
L
H
OUTPUTS
Yn
H
H
H
L
Ordering Information
PART
NUMBER
HCTS00DMSR
TEMPERATURE
RANGE
-55
o
C to +125
o
C
SCREENING
LEVEL
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
PACKAGE
14 Lead SBDIP
L
H
H
NOTE: L = Logic Level Low, H = Logic level High
HCTS00KMSR
-55
o
C to +125
o
C
14 Lead Ceramic
Flatpack
14 Lead SBDIP
Functional Diagram
An
(1, 4, 9, 12)
Yn
HCTS00D/
Sample
HCTS00K/
Sample
HCTS00HMSR
+25 C
o
+25
o
C
Sample
14 Lead Ceramic
Flatpack
Bn
(3, 6, 8, 11)
+25
o
C
Die
Die
(2, 5, 10, 13)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
Spec Number
File Number
518774
2139.2
DB NA

5962R9563701VXC Related Products

5962R9563701VXC 5962R9563701VCC
Description HCT SERIES, QUAD 2-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14 HCT SERIES, QUAD 2-INPUT NAND GATE, CDIP14
Parts packaging code DFP DIP
package instruction DFP, FL14,.3 METAL SEALED, CERAMIC, DIP-14
Contacts 14 14
Reach Compliance Code unknown unknown
Other features RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHONOLOGY RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHONOLOGY
series HCT HCT
JESD-30 code R-CDFP-F14 R-CDIP-T14
JESD-609 code e4 e4
length 9.525 mm 19.43 mm
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type NAND GATE NAND GATE
MaximumI(ol) 0.004 A 0.004 A
Number of functions 4 4
Number of entries 2 2
Number of terminals 14 14
Maximum operating temperature 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code DFP DIP
Encapsulate equivalent code FL14,.3 DIP14,.3
Package shape RECTANGULAR RECTANGULAR
Package form FLATPACK IN-LINE
power supply 5 V 5 V
Prop。Delay @ Nom-Sup 22 ns 22 ns
propagation delay (tpd) 20 ns 20 ns
Certification status Not Qualified Not Qualified
Schmitt trigger NO NO
Filter level 38535V;38534K;883S 38535V;38534K;883S
Maximum seat height 2.92 mm 5.08 mm
Maximum supply voltage (Vsup) 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V 5 V
surface mount YES NO
technology CMOS CMOS
Temperature level MILITARY MILITARY
Terminal surface GOLD GOLD
Terminal form FLAT THROUGH-HOLE
Terminal pitch 1.27 mm 2.54 mm
Terminal location DUAL DUAL
total dose 100k Rad(Si) V 100k Rad(Si) V
width 6.285 mm 7.62 mm
Base Number Matches 1 1

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