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935296863118

Description
16 I/O, PIA-GENERAL PURPOSE, PDSO24
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size492KB,37 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
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935296863118 Overview

16 I/O, PIA-GENERAL PURPOSE, PDSO24

935296863118 Parametric

Parameter NameAttribute value
MakerNXP
package instructionTSSOP-24
Reach Compliance Codeunknown
ECCN codeEAR99
JESD-30 codeR-PDSO-G24
length7.8 mm
Number of I/O lines16
Number of ports2
Number of terminals24
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Maximum seat height1.1 mm
Maximum supply voltage5.5 V
Minimum supply voltage2.3 V
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width4.4 mm
uPs/uCs/peripheral integrated circuit typePARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches1
PCA9539; PCA9539R
16-bit I
2
C-bus and SMBus low power I/O port with interrupt
and reset
Rev. 7 — 15 April 2014
Product data sheet
1. General description
The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General
Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for
I
2
C-bus/SMBus applications and was developed to enhance the NXP Semiconductors
family of I
2
C-bus I/O expanders. I/O expanders provide a simple solution when additional
I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection),
input, output and polarity inversion (active HIGH or active LOW operation) registers. The
system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each input or output is kept in the corresponding Input or
Output register. The polarity of the read register can be inverted with the Polarity inversion
register. All registers can be read by the system master.
The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the
internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are
held LOW, replacement of A2 with RESET and a different address range.
The PCA9539; PCA9539R open-drain interrupt output is activated when any input state
differs from its corresponding input port register state and is used to indicate to the system
master that an input state has changed.
The power-on reset sets the registers to their default values and initializes the device state
machine. In the PCA9539, the RESET pin causes the same reset/default I/O input
configuration to occur without de-powering the device, holding the registers and I
2
C-bus
state machine in their default state until the RESET input is once again HIGH. This input
requires a pull-up to V
DD
. In the PCA9539R however, only the device state machine is
initialized by the RESET pin and the internal general-purpose registers remain
unchanged. Using the PCA9539R RESET pin will only reset the I
2
C-bus interface should
it be stuck LOW to regain access to the I
2
C-bus. This allows the I/O pins to retain their last
configured state so that they can keep any lines in their previously defined state and not
cause system errors while the I
2
C-bus is being restored.
Two hardware pins (A0, A1) vary the fixed I
2
C-bus address and allow up to four devices to
share the same I
2
C-bus/SMBus.
2. Features and benefits
16-bit I
2
C-bus GPIO with interrupt and reset
Operating power supply voltage range of 2.3 V to 5.5 V
(5.0 V
10 % for PCA9539PW/Q900 AEC-Q100 compliant devices)
5 V tolerant I/Os
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