CS62180B
T1 Framer
Features
General Description
The CS62180B is a monolithic CMOS device
which encodes and decodes T1 framing formats.
The device supports bit-seven and B8ZS zero suppres-
sion, and bit-robbed signaling. Clear channel mode can
be selected on a per channel basis.
The serial interface has been enhanced to allow
the CS62180B to share a chip select signal and
register address space with the CS61535A,
CS61574A, and CS61575 Line Interface Units.
•
Monolithic T1 Framing Device
•
CS62180B Supports SF(D4
®
), T1DM,
ESF and SLC-96® Framing Formats
•
CS62180B Contains Updated AIS and
Carrier Loss Detection Criteria
Applications
•
•
T1 Line Cards
ISDN Primary Rate Line Cards
•
CS62180B is Pin Compatible with
DS2180A, and DS2180
Ordering Information:
CS62180B-IL 44 Pin PLCC
-40 to 85
°C
TMSYNC
TFSYNC
1
2
3
TCLK
Transmit Timing
TLCLK
11
TSER TABCD
5
9
7
6
4
8
12
Bipolar
13
Coder
TSIGSEL
TMO
TCHCLK
TSIGFR
TPOS
TNEG
CRC
TLINK
10
F-Bit Data
Yellow Alarm
Data
Selector
Transmitter
INT
CS
SCLK
SDI
SDO
SPS
14
17
18
15
16
19
Serial
Interface
Registers
40
20
VDD
VSS
33
32 RST
TEST
Control
Receive Sync
Controller
RSER
RABCD
RLINK
RLCLK
RSIGFR
RSIGSEL
RCHCLK
26
29
22
Data
DeMUX
Code Gen.
23
30
31
25
Receive
Timing
Alarm
Detect
CRC
39
37
36
Bipolar 34
Decoder 35
38
24
RLOS
RBV
RCL
RPOS
RNEG
RFER
RCLK
Synchronizer
21
28
27
Receiver
RMSYNC RFSYNC
RYEL RBL (CS2180B-IL only)
Cirrus Logic, Inc.
www.cirrus.com
Copyright
©
Cirrus Logic, Inc 2003
(All Rights Reserved)
DEC '03
DS225PP2
1
CS62180B
ABSOLUTE MAXIMUM RATINGS
Parameter
DC Supply
Input voltage, any pin
Input Current, any pin
Ambient Operating Temperature
Storage Temperature
(Referenced to GND)
(Referenced to GND)
(Note 1)
Symbol
V
DD
V
IN
I
IN
T
A
T
STG
Min
-
-1.0
-10
-40
-65
-
Typ
-
-
-
-
-
-
Max
6.0
+7
+10
85
150
260
Units
V
V
mA
°C
°C
°C
Soldering Temperature for 10 s.
-
Notes: 1. Transient current of up to 100 mA will not cause SCR latch-up.
WARNING:
Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
Parameter
DC Voltage
Supply Current
Ambient Operating Temperature
(Notes 2 and 3)
Symbol
V
DD
I
DD
T
A
Min
4.5
-
-40
Typ
5.0
3
25
Max
5.5
10
85
Units
V
mA
°C
mW
Power Consumption
(Notes 2 and 3)
P
C
-
15
85
Notes: 2. TCLK = RCLK = 1.544 MHz. If RCLK is static and RST is high, I
DD
will typically be 1.0 mA.
3. Outputs open.
DIGITAL CHARACTERISTICS (T
A
= -40 to 85 °C; V
DD
= 5.0 V
±10%;
GND = 0 V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-level Output Voltage
Low-Level Output Voltage
Output Current @ 2.4 V
Output Current @ 0.4 V
Input Leakage Current
Output Leakage Current
Input Capacitance
(Note 8)
(Note 5)
(IOUT = 1.6 mA)
(Note 6)
(Note 7)
(Note 4)
Symbol
V
IH
H
IL
V
OH
V
OL
I
OH
I
OL
I
IL
I
LO
C
IN
Min
2.0
-0.3
V
DD
- 1.0
-
-
+4
-
-
-
Typ
-
-
-
-
-
-
-
-
-
Max
V
DD
+0.3
+0.8
-
0.4
-1
-
1
1
5
Units
V
V
V
V
mA
mA
µA
µA
pF
Output Capacitance
C
OUT
-
-
7
pF
Notes: 4. V
IH
(min) = 2.2 V for V
DD
= 5.25 to 5.5 V and T
A
> 70 °C.
5. I
OUT
= -100
µA.
This guarantees the ability to drive one TTL load (V
OH
= 2.4 V @ I
OUT
= -40
µA).
6. All outputs except INT, which is open drain.
7. All outputs.
8. Applies to SDO when tristated.
2
DS225PP2
CS62180B
SWITCHING CHARACTERISTICS - SERIAL PORT
(T
A
= -40 to 85
°C;
V
DD
= 5V
±
10%; V
IH
= 2.0V; V
IL
= 0.8V; Maximum input rise & fall times of 10 ns)
Parameter
SDI to SCLK Setup
SCLK to SDI Hold
SCLK Low Time
SCLK High Time
SCLK Rise & Fall Times
CS to SCLK Set up
SCLK to CS Hold
CS Inactive Time
SCLK to SDO Valid
SCLK Rising to MSB of SDO Hold
(Note 9)
(Note 10)
(Note 9)
Symbol
t
DC
t
CDH1
t
CL
t
CH
t
R
, t
F
t
CC
t
CCH
t
CWH
t
CDV
t
CDH2
Min
50
50
250
250
-
50
50
250
-
25
Typ
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
500
-
-
-
200
-
75
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS to SDO High-Z
t
CDZ
-
-
Notes: 9. Output load capacitance = 100 pF.
10. SDO goes High-Z after rising edge of SCLK for MSB, regardless of the state of CS.
CS
t
CC
SCLK
t
DC
SDI
LSB
Control Byte
t
CDH1
t
CDH1
MSB
Data Byte
t
CH
t
CCH
t
CWH
t
CL
LSB
Serial Port Write Timing
11. In the CS62180B, data is latched on the rising edge of SCLK.
12. Shaded regions indicate
don’t care
states.
CS
t
CDZ
SCLK
t
CDV
SDO
High-Z
MSB
t
CDH2
High-Z
Serial Port Read Timing
13. Serial port write must precede a port read to provide address information.
14. SDO will go High-Z: 1) if CS returns high at anytime; 2) after outputing MSB.
DS225PP2
3
CS62180B
SWITCHING CHARACTERISTICS - TRANSMITTER
(T
A
= -40 to 85
°C;
V
DD
= 5V
±
10%; V
IH
= 2.0V; V
IL
= 0.8V; Maximum input rise & fall times of 10 ns)
Parameter
TCLK Period
TCLK Pulse Width
TCLK Rise & Fall Times
TSER, TABCD, TLINK Setup to TCLK Falling
TSER, TABCD, TLINK Hold from TCLK Falling
TFSYNC, TMSYNC Setup to TCLK Rising
TFSYNC, TMSYNC Pulse Width
Propagation Delays
TFSYNC to TMO, TSIGSEL, TSIGFR, TLCLK
TCLK Rising to TCHCLK
t
PTS
t
PTCH
-
-
-
-
75
75
ns
ns
Symbol
t
P
t
WL
, t
WH
t
F
, t
R
t
STD
t
HTD
t
STS
t
TSP
Min
250
125
-
50
50
-125
100
Typ
648
324
20
-
-
-
-
Max
-
-
-
-
-
125
-
Units
ns
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS - RECEIVER
(T
A
= -40 to 85
°C;
V
DD
= 5V
±
10%; V
IH
= 2.0V; V
IL
= 0.8V; Maximum input rise & fall times of 10 ns)
Parameter
Transition Time, All Outputs
RCLK Period
RCLK Pulse Width
RCLK Rise & Fall Times
RPOS, RNEG Setup to RCLK Falling
RPOS, RNEG Hold to RCLK Falling
Minimum RST Pulse Width on System Power Up or Restart
Propagation Delays
RCLK to RMSYNC, RFSYNC,RSIGSEL,
RSIGFR, RLCLK, RCHCLK
RCLK to RSER, RABCD, RLINK
RCLK to RYEL, RCL, RFER, RLOS, RBV
Average Reframe Time
193S
193E
T1DM
SLC-96
®
RCR.2 = 0
RCR.2 = 1
RCR.2 = 0
RCR.2 = 1
(Notes 15 and 16)
t
RS
t
RS
t
RS
t
RS
-
-
-
-
-
-
3.75
7.25
7.5
14.5
750
6.0
-
-
-
-
-
-
ms
ms
ms
ms
µs
ms
t
PRS
t
PRD
t
PRA
-
-
-
-
-
-
75
75
75
ns
ns
ns
Symbol
t
TTR
t
P
t
WL
, t
WH
t
F
, t
R
t
SRD
t
HRD
t
RST
Min
-
250
100
-
50
50
1
Typ
-
648
324
20
-
-
-
Max
20
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
µs
Notes:15. Average reframe time is the time from the rising edge of RLOS until the rising edge of RMSYNC
which updates the receiver output timing.
16. With error free data.
4
DS225PP2
CS62180B
RLOS
t
RS
RMSYNC
Old Alignment
New Alignment
Reframe Timing.
t
R
90%
10%
t
F
t
TTR
Logic 1
Logic 0
VDD - 1.0 V
0.4 V
Rise and Fall Times for RCLK & TCLK.
Transition Times for All Receiver Outputs.
t
P
TCLK
t
STD
TSER,
TABCE,
TLINK
t
TSP
TFSYNC,
TMSYNC
t
STS
TMO, TLCLK,
TSIGSEL
TSIGFR
t
PTS
TLCLK
t
PTCH
TCHCLK
t
HTD
t
WH
t
WL
Note: TMO, TLCLK, TSIGSEL and TSIGFR are generally coincident with the
rising edge of TCLK.
Transmitter Timing.
DS225PP2
5
京公网安备 11010802033920号
EEWORLD
