INTEGRATED CIRCUITS
PDI1394P21
3-port physical layer interface
Objective specification
1999 Jul 09
Philips
Semiconductors
Philips Semiconductors
Objective specification
3-port physical layer interface
PDI1394P21
1.0 FEATURES
•
Fully supports provisions of IEEE 1394–1995 Standard for high
performance serial bus and the P1394a supplement (Version
2.0)
1
•
Interface to link-layer controller supports low-cost bus-holder
isolation and optional Annex J electrical isolation
•
Full P1394a support includes:
–
Connection debounce
–
Arbitrated short reset
–
Multispeed concatenation
–
Arbitration acceleration
–
Fly-by concatenation
–
Port disable/suspend/resume
•
Data interface to link-layer controller through 2/4/8 parallel lines at
49.152 MHz
•
Low-cost 24.576 MHz crystal provides transmit, receive data at
100/200/400 Mbits/s, and link-layer controller clock at 49.152 MHz
•
Does not require external filter capacitors for PLL
•
Interoperable with link-layer controllers using 3.3 V and 5 V
supplies
•
Provides three 1394a fully-compliant cable ports at
100/200/400 Megabits per second (Mbits/s)
•
Interoperable with other Physical Layers (PHYs) using 3.3 V and
5 V supplies
•
Fully compliant with Open HCI requirements
•
Cable ports monitor line conditions for active connection to remote
node.
•
Node power class information signaling for system power
management
•
Power down features to conserve energy in battery-powered
applications include:
–
Automatic device power down during suspend
–
Device power down terminal
–
Link interface disable via LPS
–
Inactive ports powered-down
•
Cable power presence monitoring
•
Separate cable bias (TPBIAS) for each port
•
Register bits give software control of contender bit, power class
bits, link active bit, and 1394a features
•
Logic performs system initialization and arbitration functions
•
Encode and decode functions included for data-strobe bit level
encoding
•
Fully interoperable with FireWire™ implementation of IEEE Std 1394
•
Function and pin compatible with the Texas Instruments 400 Mbps
Phy TSB41LV03™
2.0 DESCRIPTION
The PDI1394P21 provides the digital and analog transceiver functions
needed to implement a three port node in a cable-based IEEE
1394–1995 and/or 1394a network. Each cable port incorporates two
differential line transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and
transmission. The PDI1394P21 is designed to interface with a Link
Layer Controller (LLC), such as the PDI1394L11 or PDI1394L21.
•
Incoming data resynchronized to local clock
•
Single 3.3 volt supply operation
•
Minimum V
DD
of 2.7 V for end-of-wire power-consuming devices
•
While unpowered and connected to the bus, will not drive TPBIAS
on a connected port, even if receiving incoming bias voltage on
that port
•
Supports extended bias-handshake time for enhanced
interoperability with camcorders
3.0 ORDERING INFORMATION
PACKAGE
80-pin plastic LQFP
TEMPERATURE RANGE
0°C to +70°C
OUTSIDE NORTH AMERICA
PDI1394P21 BE
NORTH AMERICA
PDI1394P21 BE
PKG. DWG. #
SOT315-1
1.
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
1999 Jul 09
2
Philips Semiconductors
Objective specification
3-port physical layer interface
PDI1394P21
4.0 PIN CONFIGURATION
PLLGND
PLLGND
PLLVDD
/RESET
AGND
DGND
DGND
AGND
DVDD
NC
XO
NC
AGND
61
60 AGND
59 TPBIAS2
58 TPA2+
57 TPA2–
56 TPB2+
55 TPB2–
54 AVDD
53 TPBIAS1
52 TPA1+
51 TPA1–
50 TPB1+
49 TPB1–
48
AVDD
47 AVDD
46
TPBIAS0
45 TPA0+
44 TPA0–
43 TPB0+
42 TPB0–
41 AGND
21
DGND
22
C/LKON
23
PC0
24
PC1
25
PC2
26
/ISO
27
CPS
28
DGND
29
DVDD
30
DVDD
31
NC
32
TEST1
33
TEST0
34
AVDD
35
AVDD
36
AGND
37
AGND
38
AGND
39
AGND
40
AGND
DVDD
DVDD
AVDD
63
AVDD
62
R1
R0
XI
80
LREQ
SYSCLK
DGND
CTL0
CTL1
DVDD
D0
D1
NC
1
2
3
4
5
6
7
8
9
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
D2 10
D3
11
PDI1394P21
D4 12
D5 13
D6 14
D7 15
DGND 16
CNA 17
PD 18
LPS 19
DGND 20
SV001742
5.0 PIN DESCRIPTION
Name
AGND
AVDD
Pin Type
Supply
Supply
Pin Numbers
36, 37, 38, 39, 40,
41, 60, 61, 64, 65
34, 35, 47, 48, 54,
62, 63
I/O
—
—
Description
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
Analog circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1
µF
and 0.001
µF.
Lower frequency 10
µF
filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and DVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
Cable Power Status input. This terminal is normally connected to cable
power through a 370–410 kΩ resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
Control I/Os. These bi-directional signals control communication
between the PDI1394P21 and the LLC. Bus holders are built into
these terminals.
CNA
CPS
CMOS
CMOS
17
27
O
I
CTL0,
CTL1
CMOS 5V tol
4, 5
I/O
1999 Jul 09
3
Philips Semiconductors
Objective specification
3-port physical layer interface
PDI1394P21
Name
C/LKON
Pin Type
CMOS 5V tol
22
Pin Numbers
I/O
I/O
Description
Bus Manager Contender programming input and link-on output. On
hardware reset, this terminal is used to set the default value of the
contender status indicated during self-ID. Programming is done by tying
the terminal through a 10kΩ resistor to a high (contender) or low (not
contender). The resistor allows the link-on output to override the input.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is deasserted low when
the LPS input terminal is active.
DGND
D0–D7
DVDD
Supply
CMOS 5V tol
Supply
3, 16, 20, 21, 28,
70, 80
7, 8, 10, 11, 12, 13,
14, 15
6, 29, 30, 68, 69, 79
—
I/O
—
Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
Data I/Os. These are bi-directional data signals between the
PDI1394P21 and the LLC. Bus holders are built into these terminals.
Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1
µF
and 0.001
µF.
Lower frequency 10
µF
filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and AVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
Link interface isolation control input. This terminal controls the operation
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1395
is implemented between the PDI1394P21 and LLC, the /ISO terminal
should be tied low to enable the differentiation logic. If no isolation barrier
is implemented (direct connection), or bus holder isolation is
implemented, the /ISO terminal should be tied high to disable the
differentiation logic.
Link Power Status input. This terminal is used to monitor the power
status of the LLC, and is connected to either the V
DD
supplying the link
layer controller through a 1kΩ resistor, or to a pulsed output which is
active when the LLC is powered. The pulsed output is useful when using
an isolation barrier. If this input is low for more than 25
ms,
the LLC is
considered powered down. If this input is high for more than 20 ns, the
LLC is considered powered up. If the LLC is powered-down, the
PHY–LLC interface is disabled, and the PDI1394P21 performs only the
basic repeater functions required for network initialization and operation.
Bus holder is built into this terminal.
LLC Request input. The LLC uses this input to initiate a service request
to the PDI1394P21. Bus holder is built into this terminal.
These pins are not internally connected, and consequently are “don’t
cares”. Other vendor’s pin compatible chips may require connections
and external circuitry on these pins.
Power Class programming inputs. On hardware reset, these inputs set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 18 for encoding.
Power Down input. A logic high on this terminal turns off all internal
circuitry except the cable-active monitor circuits which control the CNA
output. Bus holder is built into this terminal. For more information, refer to
Section 17.3
PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1
µF
and 0.001
µF.
Lower frequency 10
µF
filtering capacitors are also
recommended. These supply terminals are separated from DVDD and
AVDD internal to the device to provide noise isolation. They should be
tied at a low impedance point on the circuit board.
/ISO
CMOS
26
I
LPS
CMOS 5V tol
19
I
LREQ
NC
CMOS 5V tol
No Connect
1
9, 31, 71, 72
I
—
PC0, PC1,
PC2
CMOS 5V tol
23, 24, 25
I
PD
CMOS 5V tol
18
I
PLLGND
PLLVDD
Supply
Supply
74, 75
73
—
—
1999 Jul 09
4
Philips Semiconductors
Objective specification
3-port physical layer interface
PDI1394P21
Name
/RESET
Pin Type
CMOS 5V tol
78
Pin Numbers
I/O
I
Description
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to V
DD
is provided so only an external
delay capacitor in parallel with a resistor is required for proper power-up
operation. For more information, refer to Section 17.3. This input is
otherwise a standard logic input, and can also be driven by an
open-drain type driver.
Current setting resistor terminals. These terminals are connected to
an external resistance to set the internal operating currents and
cable driver output currents. A resistance of 6.34 kΩ
±1%
is required to
meet the IEEE Std 1394–1995 output voltage limits.
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
Test control input. This input is used in manufacturing tests of the
PDI1394P21. For normal use, this terminal should be tied to GND.
Test control input. This input is used in manufacturing tests of the
PDI1394P21. For normal use, this terminal should be tied to GND.
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
g
g
matched and as short as possible to the external load resistors and to
the cable connector.
R0, R1
Bias
66, 67
—
SYSCLK
TEST0
TEST1
TPA0+,
TPA1+,
TPA2+
TPA0–,
TPA1–,
TPA2–
TPB0+,
TPB1+,
TPB2+
TPB0–,
TPB1–,
TPB2–
TPBIAS0,
TPBIAS1,
TPBIAS2
CMOS
CMOS
CMOS
Cable
2
33
32
45, 52, 58
O
I
I
I/O
Cable
44, 51, 57
I/O
Cable
43, 50, 56
I/O
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
g
g
matched and as short as possible to the external load resistors and to
the cable connector.
Twisted-pair bias output. This provides the 1.86V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. Each of these terminals must be decoupled with a
0.3
µF–1 µF
capacitor to ground.
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case).
Cable
42, 49, 55
I/O
Cable
46, 53, 59
I/O
XO, XI
Crystal
77, 76
—
1999 Jul 09
5
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