The PCM61P is an 18-bit totally pin compatible per-
formance replacement for the popular 16-bit PCM56P.
With the addition of two extra bits, lower max THD+N
(–92dB; PCM61P-K) can be achieved in audio applica-
tions already using the PCM56P. The PCM61P is
complete with internal reference and output op amp and
requires no external parts to function as an 18-bit DAC.
The PCM61P is capable of an 8-times oversampling
rate (single channel) and meets all of its specifications
without an external output deglitcher.
The PCM61P comes in a small, reliable 16-pin plastic
DIP package that has passed operating life tests under
simultaneous high temperature, high humidity and high
pressure testing.
VREF
Ref
MSB Adj
R
F
Control
Logic
Latch Enable
_
Data
Serial-To-Parallel
Shift Register
V
OUT
+
18-Bit
I
OUT
DAC
I
OUT
SJ
Clock
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sample frequency (4 x 44.1kHz; 4 times oversampling). (5) Bipolar zero, using A-weighted filter. (6) This is the combined drift error due to gain, offset, and linearity over
temperature. (7) All positive and all negative supply pins must be tied together respectively.
®
PCM61P
2
PIN ASSIGNMENTS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FUNCTION
–V
S
LOG COM
+V
L
NC
CLK
LE
DATA
–V
L
V
OUT
RF
SJ
ANA COM
I
OUT
MSB ADJ
TRIM
+V
S
DESCRIPTION
Analog Negative Supply
Logic Common
Logic Positive Supply
No Connection
Clock Input
Latch Enable Input
Serial Data Input
Logic Negative Supply
Voltage Output
Feedback Resistance
Summing Junction
Analog Common
Current Output
MSB Adjustment Terminal
MSB Trim-pot Terminal
Analog Positive Supply
CONNECTION DIAGRAM
–5V
1µF
–V
S
Logic
Com
+V
L
1
2
3
4
5
6
7
8
Control
Logic
and
Level
Shifting
Circuit
18-Bit Serial
to Parallel
Conversion
18-Bit
DAC Latch
18-Bit
I
OUT
DAC
16
+V
S
+5V
1µF
15
Trim
(1)
+5V
1µF
14
MSB Adjust
13
12
11
10
SJ
RF
I
OUT
(1)
NC
CLK
LE
Data
Analog
Common
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltages ......................................................................
±16VDC
Input Logic Voltage ............................................................. –1V to V
S
/+V
L
Power Dissipation .......................................................................... 850mW
Operating Temperature Range ......................................... –25°C to +70°C
Storage Temperature Range .......................................... –60°C to +100°C
Lead Temperature (soldering, 10s) ............................................... +300°C
–5V
1µF
–V
L
–
+
Analog
V
OUT
Output
9
(±3V)
NOTE: (1) MSB error (Bipolar Zero differential linearity error) can be
adjusted to zero using the external circuit shown in Figure 4.
PACKAGE INFORMATION
PRODUCT
PCM61P-P
PCM61P-J
PCM61P-K
PACKAGE
16-Pin Plastic DIP
16-Pin Plastic DIP
16-Pin Plastic DIP
PACKAGE DRAWING
NUMBER
(1)
180
180
180
DIGITAL INPUT
Binary Two’s
Complement (BTC)
1FFFF Hex
00000 Hex
3FFFF Hex
20000 Hex
ANALOG OUTPUT
Voltage (V)
V
OUT
Mode
–0.99999237
0.00000000
+0.00000763
+1.00000000
Current (mA)
I
OUT
Mode
+2.99997711
0.00000000
–0.00002289
–3.00000000
DAC Output
+FS
BPZ
BPZ – 1LSB
–FS
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
TABLE I. PCM61P Input/Output Relationships.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
PCM61P
P16 (Clock)
P18 (Data)
1
MSB
2
3
4
10
11
12
13
14
15
16
17
18
LSB
1
P17 (Latch Enable)
NOTES: (1) If clock is stopped between input of 18-bit data words, latch enable (LE) must remain low until after the first clock of the next 18-bit data word stream.
(2) Data format is binary two‘s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch enable (LE) must remain
low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going negative.
FIGURE 1. PCM61P Timing Diagram.
>25ns
Data
Input
LSB
>15ns >15ns
Clock
Input
>25ns
>60ns
>15ns
Latch
Enable
> One Clock Cycle
> One Clock Cycle
>25ns
>5ns
MSB
MSB ERROR ADJUSTMENT PROCEDURE
(OPTIONAL)
The MSB error of the PCM61P can be adjusted to make the
differential linearity error (DLE) at BPZ essentially zero. This
is important when the signal output levels are very low,
because zero crossing noise (DLE at BPZ) becomes very
significant when compared to the small code changes occur-
ring in the LSB portion of the converter.
To statically adjust DLE at BPZ, refer to the circuit shown in
Figure 3 or the PCM61P connection diagram.
Differential linearity error at bipolar zero and THD are guar-
anteed to meet data sheet specifications without any external
adjustment. However, a provision has been made for an
optional adjustment of the MSB linearity point, which makes
it possible to eliminate DLE error at BPZ. Two procedures are
given to allow either static or dynamic adjustment. The
dynamic procedure is preferred because of the difficulty
associated with the static method (accurately measuring 16-
bit LSB steps).
After allowing ample warm-up time (5-10 minutes) to assure
stable operation of the PCM61P, select input code 3FFFF
hexadecimal (all bits on except the MSB). Measure the output
voltage using a 6-1/2 digit voltmeter and record it. Change the
digital input code to 00000 hexadecimal (all bits off except the
MSB). Adjust the 100kΩ potentiometer to make the output
read 22.9µV more than the voltage reading of the previous
code (a 1LSB step = 22.9µV). A much simpler method is to
dynamically adjust the DLE at BPZ. Assuming the device has
been installed in a digital audio application circuit, send the
appropriate digital input to produce a –60dB level sinusoidal
output, then adjust the 100kΩ potentiometer until a minimum
level of distortion is observed.
FIGURE 2. PCM61P Setup and Hold Timing Diagram.
MAXIMUM CLOCK RATE
The maximum clock rate of 16.9MHz for the PCM61P is
derived by multiplying the standard audio sample rate of
44.1kHz times sixteen (16
x
oversampling) times the standard
audio word bit length of 24 (44.1kHz
x
16
x
24 = 16.9MHz).
Note that this clock rate accommodates a 24-bit word length,
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