Typical at +25°C, and nominal power supply voltages
±5V,
unless otherwise noted.
PCM56U, PCM56P-J, -K
PARAMETER
DIGITAL INPUT
Resolution
Digital Inputs
(1)
: V
IH
V
IL
I
IH
, V
IN
= +2.7V
I
IL
, V
IN
= +0.4V
Input Clock Frequency
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error
Bipolar Zero Error
Differential Linearity Error
Noise (rms, 20Hz to 20kHz) at Bipolar Zero (V
OUT
models)
TOTAL HARMONIC DISTORTION
V
O
=
±FS
at f = 991Hz: PCM56P-K
PCM56P-J
PCM56P, PCM56U
PCM56P-L
V
O
= –20dB at f = 991Hz: PCM56P-K
PCM56P-J
PCM56P, PCM56U
PCM56P-L
V
O
= –60dB at f = 991Hz: PCM56P-K
PCM56P-J
PCM56P, PCM56U
PCM56P-L
MONOTONICITY
DRIFT
(0°C to +70°C)
Total Drift
(3)
Bipolar Zero Drift
SETTLING TIME
(to
±0.006%
of FSR)
Voltage Output: 6V Step
1LSB
Slew Rate
Current Output, 1mA Step: 10Ω to 100Ω Load
1kΩ Load
(4)
WARM-UP TIME
OUTPUT
Voltage Output Configuration: Bipolar Range
Output Current
Output Impedance
Short Circuit Duration
Current Output Configuration:
Bipolar Range (±30%)
Output Impedance (±30%)
POWER SUPPLY REQUIREMENTS
(5)
Voltage: +V
S
and +V
L
–V
S
and –V
L
Supply Drain (No Load): +V (+V
S
and +V
L
= +5V)
–V (–V
S
and –V
L
= –5V)
+V (+V
S
and +V
L
= +12V)
–V (–V
S
and –V
L
= –12V)
Power Dissipation: V
S
and V
L
=
±5V
V
S
and V
L
=
±12V
TEMPERATURE RANGE
Specification
Operation
Storage
1
±3.0
0.10
Indefinite to Common
±1.0
1.2
+4.75
–4.75
+5.00
–5.00
+10.00
–25.0
+12.0
–27.0
175
468
+13.2
–13.2
+17.0
–35.0
MIN
TYP
16
+2.4
0
+V
L
+0.8
+1.0
–50
MAX
UNITS
Bits
V
V
µA
µA
MHz
10.0
±2.0
±30
±0.001
6
–94
–94
–94
–94
–75
–75
–75
–75
–35
–35
–35
–35
15
±25
±4
1.5
1.0
10
350
350
–92
–88
–82
–80
–74
–68
–68
–60
–34
–28
–28
–20
%
mV
% of FSR
(2)
µV
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
ppm of FSR/°C
ppm of FSR/°C
µs
µs
V/µs
ns
ns
Min
V
mA
Ω
±2.0
mA
kΩ
V
V
mA
mA
mA
mA
mW
mW
°C
°C
°C
260
0
–25
–60
+70
+70
+100
NOTES: (1) Logic input levels are TTL/CMOS-compatible. (2) FSR means full-scale range and is equivalent to 6V (±3V) for PCM56 in the V
OUT
mode. (3) This is the
combined drift error due to gain, offset, and linearity over temperature. (4) Measured with an active clamp to provide a low impedance for approximately 200ns. (5) All
specifications assume +V
S
connected to +V
L
and –V
S
connected to –V
L
. If supplies are connected separately, –V
L
must not be more negative than –V
S
supply voltage
to assure proper operation. No similar restriction applies to the value of +V
L
with respect to +V
S
.
®
PCM56
2
ABSOLUTE MAXIMUM RATINGS
DC Supply Voltages ......................................................................
±16VDC
Input Logic Voltage ............................................................ –1V to +V
S
/+V
L
Power Dissipation .......................................................................... 850mW
Operating Temperature ..................................................... –25°C to +70°C
Storage Temperature ...................................................... –60°C to +100°C
Lead Temperature (soldering, 10s) ................................................ +300°C
PACKAGE INFORMATION
MODEL
PCM56U
PCM56P
PCM56P-J
PCM56P-K
PCM56P-L
PACKAGE
16-Pin SOIC
16-Pin Plastic DIP
16-Pin Plastic DIP
16-Pin Plastic DIP
16-Pin Plastic DIP
PACKAGE DRAWING
NUMBER
(1)
211
180
180
180
180
PIN ASSIGNMENTS
PIN
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
DESCRIPTION
Analog Negative Supply
Logic Common
Logic Positive Supply
No Connection
Clock Input
Latch Enable Input
Serial Data Input
Logic Negative Supply
Voltage Output
Feedback Resistor
Summing Junction
Analog Common
Current Output
MSB Adjustment Terminal
MSB Trim-pot Terminal
Analog Positive Supply
MNEMONIC
–V
S
LOG COM
+V
L
NC
CLK
LE
DATA
–V
L
V
OUT
RF
SJ
ANA COM
I
OUT
MSB ADJ
TRIM
+V
S
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
CONNECTION DIAGRAM
–5V
1µF
–V
S
Logic
Common
+V
L
1
2
16
16-Bit
DAC Latch
–V
S
+5V
1µF
15 Trim
(1)
16-Bit Serial
to Parallel
Conversion
16-Bit
I
OUT
DAC
14 MSB Adjust
(1)
13
12
11
10
9
V
OUT
(±3.0V)
SJ
RF
Analog
Output
I
OUT
Analog
Common
+5V
1µF
3
4
5
6
7
8
NC
CLK
LE
Data
–5V
1µF
–V
L
Control
Logic and
Level
Shifting
Circuit
NOTE: (1) MSB error (Bipolar Zero differential linearity error)
can be adjusted to zero using the external circuit shown in Figure 6.
®
3
PCM56
DISCUSSION OF
SPECIFICATIONS
Digital Input
0111...1111
0111...1110
0000...0010
0000...0001
0000...0000
1111...1111
1111...1110
1000...0001
1000...0000
Offset
Drift
All Bits On
Gain
Drift
The PCM56 is specified to provide critical performance
criteria for a wide variety of applications. The most critical
specifications for D/A converter in audio applications are
Total Harmonic Distortion, Differential Linearity Error,
Bipolar Zero Error, parameter shifts with time and
temperature, and settling time effects on accuracy.
The PCM56 is factory-trimmed and tested for all critical key
specifications.
The accuracy of a D/A converter is described by the transfer
function shown in Figure 1. Digital input to analog output
relationship is shown in Table I. The errors in the D/A
converter are combinations of analog errors due to the linear
circuitry, matching and tracking properties of the ladder and
scaling networks, power supply rejection, and reference
errors. In summary, these errors consist of initial errors
including Gain, Offset, Linearity, Differential Linearity, and
Power Supply Sensitivity. Gain drift over temperature rotates
the line (Figure 1) about the bipolar zero point and Offset
drift shifts the line left or right over the operating temperature
range. Most of the Offset and Gain drift with temperature or
time is due to the drift of the internal reference zener diode.
The converter is designed so that these drifts are in opposite
directions. This way the Bipolar Zero voltage is virtually
unaffected by variations in the reference voltage.
DIGITAL INPUT CODES
The PCM56 accepts serial input data (MSB first) in the
Binary Two’s Complement (BTC) form. Refer to Table I
for input/output relationships.
DIGITAL INPUT
Binary Two’s
Complement (BTC)
7FFF Hex
8000 Hex
0000 Hex
FFFF Hex
ANALOG OUTPUT
Voltage (V),
V
OUT
Mode
+2.999908
–3.000000
0.000000
–0.000092
Current (mA),
I
OUT
Mode
–0.999970
+1.000000
0.000000
+0.030500µA
Bipolar
Zero
–FSR/2
Analog Output
(+FSR/2) –1LSB
* See Table I for digital code definitions.
FIGURE 1. Input vs Output for an Ideal Bipolar D/A Con-
verter.
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect accuracy.
The PCM56 power supply sensitivity is shown by Figure 2.
Normally, regulated power supplies with 1% or less ripple
are recommended for use with the DAC. See also Power
Supply Connections paragraph in the Installation and
Operating Instructions section.
SETTLING TIME
Settling time is the total time (including slew time) required
for the output to settle within an error band around its final
value after a change in input (see Figure 3).
Settling times are specified to
±0.006%
of FSR: one for a
large output voltage change of 6V and one for a 1LSB
change. The 1LSB change is measured at the major carry
(0000 hex to ffff hex), the point at which the worst-case
settling time occurs.
DAC Output
+ Full Scale
– Full Scale
Bipolar Zero
Zero –1LSB
86
Power Supply Rejection (dB)
TABLE I. Digital Input to Analog Output Relationship.
BIPOLAR ZERO ERROR
Initial Bipolar Zero Error (Bit 1 “on” and all other bits “off”)
is the deviation from 0V out and is factory-trimmed to
typically
±30mV
at +25°C.
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error (DLE) is the deviation from an
ideal 1LSB change from one adjacent output state to the
next. DLE is important in audio applications because
excessive DLE at Bipolar Zero (at the “major carry”) can
result in audible crossover distortion for low level output
signals. Initial DLE on the PCM56 is factory trimmed to
typically
±0.001%
of FSR. The MSB DLE is adjustable to
zero using the circuit shown in Figure 6.
®
80
74
68
62
56
52
46
40
34
28
1
Negative Supplies
Positive Supplies
10
100
1k
10k
100k
Frequency (Hz)
FIGURE 2. Power Supply Sensitivity.
PCM56
4
1.0
Accuracy
Percent Full-Scale Range (%)
0.3
0.1
0.03
0.01
R
L
= 200Ω
0.003
0.001
0.01
Current
Output
Mode
Voltage
Output
Mode
The THD is defined as the ratio of the square root of the sum
of the squares of the values of the harmonics to the value of
the fundamental input frequency and is expressed in percent
or dB. The rms value of the PCM56 error referred to the
input can be shown to be:
∈
rms
=
1/n
∑
n
i
=
1
E (i )
+
E (i)
L
Q
2
(1)
0.1
Settling Time (µs)
1.0
10.0
where n is the number of samples in one cycle of any given
sine wave, E
L
(i) is the linearity error of the PCM56 at each
sampling point, and E
Q
(i) is the quantization error at each
sampling point. The THD can then be expressed as:
FIGURE 3. Full Scale Range Settling Time vs Accuracy.
STABILITY WITH TIME AND TEMPERATURE
The parameters of a D/A converter designed for audio
applications should be stable over a relatively wide
temperature range and over long periods of time to avoid
undesirable periodic readjustment. The most important
parameters are Bipolar Zero Error, Differential Linearity
Error, and Total Harmonic Distortion. Most of the Offset
and Gain drift with temperature or time is due to the drift of
the internal reference zener diode. The PCM56 is designed
so that these drifts are in opposite directions so that the
Bipolar Zero voltage is virtually unaffected by variations in
the reference voltage. Both DLE and THD are dependent
upon the matching and tracking of resistor ratios and upon
V
BE
and h
FE
of the current-source transistors. The PCM56
was designed so that any absolute shift in these components
has virtually no effect on DLE or THD. The resistors are
made of identical links of ultra-stable nichrome thin-film.
The current density in these resistors is very low to further
enhance their stability.
DYNAMIC RANGE
The Dynamic Range is a measure of the ratio of the smallest
signals the converter can produce to the full-scale range and
is usually expressed in decibels (dB). The theoretical dynamic
range of a converter is approximately 6
x
n, or about 96dB
of a 16-bit converter. The actual, or useful, dynamic range is
limited by noise and linearity errors and is therefore somewhat
less than the theoretical limit. However, this does point out
that a resolution of at least 16 bits is required to obtain a
90dB minimum dynamic range, regardless of the accuracy
of the converter. Another specification that is useful for
audio applications is Total Harmonic Distortion.
TOTAL HARMONIC DISTORTION
THD is useful in audio applications and is a measure of the
magnitude and distribution of the Linearity Error, Differential
Linearity Error, and Noise, as well as Quantization Error. To
be useful, THD should be specified for both high level and
low level input signals. This error is unadjustable and is the
most meaningful indicator of D/A converter accuracy for
audio applications.
5
THD
= ∈
rms
/ E
rms
1 /n
∑
n
i
=
1
E (i )
+
E (i)
L
Q
2
(2)
X
=
E
rms
where E
rms
is the rms signal-voltage level.
100%
This expression indicates that, in general, there is a correlation
between the THD and the square root of the sum of the
squares of the linearity errors at each digital word of interest.
However, this expression does not mean that the worst-case
linearity error of the D/A is directly correlated to the THD.
For the PCM56 the test period was chosen to be 22.7µs
(44.1kHz), which is compatible with the EIAJ STC-007
specification for PCM audio. The test frequency is 991Hz
and the amplitude of the input signal is 0dB, –20dB, and
–60dB down from full scale.
Figure 4 shows the typical THD as a function of output
voltage.
Figure 5 shows typical THD as a function of frequency.
京公网安备 11010802033920号
EEWORLD
