PCM1804
SLES022A – DECEMBER 2001
FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz
STEREO A/D CONVERTER
FEATURES
D
24-Bit Delta-Sigma Stereo A/D Converter
D
High Performance:
– Dynamic Range: 112 dB (Typically)
– SNR: 111 dB (Typically)
– THD+N: -102 dB (Typically)
High Performance Linear Phase antialias
Digital Filter:
– Pass-Band Ripple:
±0.005
dB
– Stop-Band Attenuation: –100 dB
Fully Differential Analog Input:
±2.5
V
Audio Interface: Master or Slave Mode
Selectable
Data Formats: Left Justified, I
2
S, Standard
24-Bit and DSD
Function:
– Peak Detection
– Low-Cut Filter (HPF): –3 dB at 1 Hz,
f
S
= 48 kHz
Sampling Rate up to 192 kHz
System Clock: 128 f
S
, 256 f
S
, 384 f
S
, 512 f
S
, or
768 f
S
Dual Power Supplies:
– 5 V for Analog
– 3.3 V for Digital
Power Dissipation: 225 mW
PACKAGE
DRAWING
NUMBER
28DB
D
Small 28-Pin SSOP
D
DSD Output: 1 Bit, 64 f
S
D
Lead-Free Product
APPLICATIONS
D
AV Amp
D
MD Player
D
Digital VTR
D
Digital Mixer
D
Digital Recorder
DESCRIPTION
The PCM1804 is a high-performance single chip stereo
A/D converter with full differential analog voltage input.
The PCM1804 uses a precision delta-sigma modulator
and includes a linear phase antialias digital filter and
HPF (low-cut filter) that removes dc offset of the input
signal. The PCM1804 is suitable for a wide variety of
mid-to-high grade consumer and professional
applications, where excellent performance and 5-V
analog supply and 3.3-V digital power supply operation
are required. The PCM1804 can achieve both PCM
audio and DSD format due to precision delta-sigma
modulator. The PCM1804 is fabricated on an advanced
CMOS process and is available in small 28-pin SSOP
package.
D
D
D
D
D
D
D
D
D
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
OPERATING
TEMPERATURE RANGE
–10°C to 70°C
10°C
PACKAGE
MARKING
PCM1804DB
ORDERING NUMBER
PCM1804DB
PCM1804DB
28-Lead
28 Lead SSOP
PCM1804DBR
TRANSPORT
MEDIA
Tube
Tape and Reel
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication
Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2001, Texas Instruments Incorporated
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1
PCM1804
SLES022A – DECEMBER 2001
pin assignments
PCM1804 PACKAGE
(TOP VIEW)
V
REF
L
AGNDL
V
COM
L
V
IN
L+
V
IN
L–
FMT0
FMT1
S/M
OSR0
OSR1
OSR2
BYPAS
DGND
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
REF
R
AGNDR
V
COM
R
V
IN
R+
V
IN
R–
AGND
V
CC
OVFL
OVFR
RST
SCKI
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
functional block diagram
OSR0
SCKI
CLK
Control
OSR1
OSR2
VINL+
VINL–
VCOML
AGNDL
VREFL
Delta-Sigma
Modulator (L)
Decimation
Filter (L)
HPF
S/M
FMT0
FMT1
VREFL
Serial
Output
Interface
VREFR
LRCK/DSDBCK
BCK/DSDL
DATA/DSDR
VREFR
AGNDR
VCOMR
VINR+
VINR–
Delta-Sigma
Modulator (R)
Decimation
Filter (R)
HPF
OVFL
OVFR
BYPAS
Power Supply
RST
VCC AGND
DGND
VDD
2
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PCM1804
SLES022A – DECEMBER 2001
Terminal Functions
TERMINAL
NAME
AGND
AGNDL
AGNDR
BCK/DSDL
BYPAS
DATA/DSDR
DGND
FMT0
FMT1
LRCK/DSDBCK
OSR0
OSR1
OSR2
OVFL
OVFR
RST
SCKI
S/M
VCC
VCOML
VCOMR
VDD
VINL–
VINL+
VINR–
VINR+
PIN
23
2
27
16
12
15
13
6
7
17
9
10
11
21
20
19
18
8
22
3
26
14
5
4
24
25
I/O
–
–
–
I/O
I
O
–
I
I
I/O
I
I
I
O
O
I
I
I
–
–
–
–
I
I
I
I
Analog ground
Analog ground for VREFL
Analog ground for VREFR
Bit clock input/output in PCM mode. L-channel audio data output in DSD mode. §
HPF bypass control. High: HPF disable, Low: HPF enable§
L-channel and R-channel audio data output in PCM mode. R-channel audio data output in DSD mode.
(DSD output, when DSD mode)
Digital ground
Audio data format 0. See Table 5†
Audio data format 1. See Table 5†
Sampling clock input / output in PCM and DSD mode. §
Oversampling ratio 0. See Table 1 and Table 2†
Oversampling ratio 1. See Table 1 and Table 2†
Oversampling ratio 2. See Table 1 and Table 2†
Overflow signal of L-channel in PCM mode. This is available in PCM mode only.
Overflow signal of R-channel in PCM mode. This is available in PCM mode only.
Reset, power down input, active low†
System clock input; 128 fS, 256 fS, 384 fS, 512 fS or 768 fS.‡
Master / slave mode selection. See Table 4.†
Analog power supply
L-channel analog common mode voltage (2.5 V)
R-channel analog common mode voltage (2.5 V)
Digital power supply
L-channel analog input, negative pin
L-channel analog input, positive pin
R-channel analog input, negative pin
R-channel analog input, positive pin
DESCRIPTIONS
VREFL
1
–
L-channel voltage reference output, requires capacitors for decoupling to AGND
VREFR
28
–
R-channel voltage reference output, requires capacitors for decoupling to AGND
† Schmitt-trigger input with internal pulldown (51 kΩ typically), 5-V tolerant.
‡ Schmitt-trigger input, 5-V tolerant.
§ Schmitt-trigger input
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3
PCM1804
SLES022A – DECEMBER 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage: V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 V
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 V
Ground voltage differences: AGND, AGNDL, AGNDR, DGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±0.1
V
Digital input voltage: FMT0, FMT1, S/M, OSR0, OSR1, OSR2, SCKI, RST . . . . . . . . . . . . . . . . . . . .
–0.3
V to 6.5 V
BYPAS, DATA/DSDR, BCK/DSDL, LRCK/DSDBCK,
OVFL, OVFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
DD
+ 0.3 V)
Analog input voltage: V
REF
L, V
REF
R, V
COM
L, V
COM
R, V
IN
L+, V
IN
R+, V
IN
L–, V
IN
R–
. . .
–0.3 V to (V
CC
+ 0.3 V)
Input current (any pins except supplies)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±10
mA
Ambient temperature under bias, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–40°C to 125°C
Storage temperature, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–55°C to 150°C
Junction temperature, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150°C
Lead temperature (soldering)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
260°C, 5 s
Package temperature (IR reflow, peak)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
260°C, 10 s
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
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PCM1804
SLES022A – DECEMBER 2001
electrical characteristics, all specifications at T
A
= 25°C, V
CC
= 5 V, V
DD
= 3.3 V, master mode,
single-speed mode, f
S
= 48 kHz, system clock = 256 f
S
, 24-bit data (unless otherwise noted)
PCM1804DB
PARAMETER
Resolution
DATA FORMAT
Audio data interface format
Audio data bit length
Audio data format
DIGITAL INPUT/OUTPUT
Logic family
See Notes 1 and 2
VIH
VIL
IIH
High-level
High level input voltage
Low-level input voltage
See Note 3
See Notes 1, 2, and 3
VIN = VDD,
VIN = VDD,
VIN = VDD,
VIN = 0 V,
VIN = 0 V,
IOH = –1 mA,
IOL = 1 mA,
See Note 1
See Note 2
See Note 3
See Notes 1 and 2
See Note 3
See Note 4
See Note 5
32
256 fS, Single rate, See Note 5
384 fS, Single rate, See Note 5
512 fS, Single rate, See Note 5
System clock frequency
768 fS, Single rate, See Note 5
256 fS, Dual rate,
384 fS, Dual rate,
See Note 6
See Note 6
12.288
18.432
24.576
36.864
24.576
36.864
24.576
36.864
±3
±4
HPF bypass
±0.2
%/FSR
%/FSR
%/FSR
MHz
2.4
0.4
192
65
TTL compatible
2
2
5.5
VDD
0.8
100
±10
±100
±10
±50
µA
A
VDC
VDC
kHz
µA
VDC
VDC
Standard, I2S,
left justified
24-bits
MSB first,
2s complement, DSD
TEST CONDITIONS
MIN
TYP
24
MAX
UNIT
Bits
High level input
High-level in ut current
IIL
VOH
VOL
fS
Low-level
Low level input current
High-level output voltage
Low-level output voltage
Sampling frequency
CLOCK FREQUENCY
128 fS, Quad rate, See Note 7
192 fS, Quad rate, See Note 7
DC ACCURACY
Gain mismatch channel-to-channel
Gain error (VIN = –0.5 dB)
Bipolar zero error
NOTES: 1. Pins 6–11, 19: FMT0, FMT1, S/M, OSR0, OSR1, OSR2, RST (Schmitt-trigger input with internal pulldown (51 kΩ typically), 5 V
tolerant)
2. Pin 18: SCKI (Schmitt-trigger input, 5 V tolerant)
3. Pins 12, 16–17: BYPAS, BCK/DSDL, LRCK/DSDBCK (in slave mode, Schmitt-trigger input)
4. Pins 15–17, 20, and 21: DATA/DSDR, BCK/DSDL, LRCK/DSDBCK (in master mode), OVFR, OVFL
5. Single rate, fS = 48 kHz
6. Dual rate, fS = 96 kHz
7. Quad rate, fS = 192 kHz
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5
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