circuit which includes stereo digital-to-analog con-
verters and support circuitry in a small SSOP-28
package. The data converters utilize Burr-Brown’s
enhanced multi-level delta-sigma architecture, which
employs 4th-order noise shaping and 8-level ampli-
tude quantization to achieve excellent dynamic per-
formance and improved tolerance to clock jitter.
The PCM1737 accepts industry standard audio data
formats with 16- to 24-bit data, providing easy
interfacing to audio DSP and decoder chips. Sam-
pling rates up to 192kHz are supported. A full set
of user-programmable functions are accessible through
a 4-wire serial control port which supports register
write and read back functions.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
= 44.1kHz) and 24-bit data, unless otherwise noted.
PCM1737E
PARAMETER
RESOLUTION
DATA FORMAT
Audio Data Interface Formats
Audio Data Bit Length
Audio Data Format
System Clock Frequency
Sampling Frequency (f
S
)
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level
V
IH
V
IL
Input Logic Current
I
IH
I
IL
I
IH(1)
I
IL(1)
Output Logic Current, Pin 25 (MDO)
I
IZH
I
IZL
Output Logic Level
V
OH(2)
V
OL(2)
V
OH(3)
V
OL(3)
DYNAMIC PERFORMANCE
(4)
THD+N, V
OUT
= 0dB
User Selectable
User Selectable
CONDITIONS
MIN
TYP
24
Standard, I
2
S, Left-Justified
16-, 18-, 20-, 24-Bit
MSB-First, Binary Two’s Complement
128, 192, 256, 384, 512, 768f
S
10
200
TTL-Compatible
2.0
0.8
V
IN
= V
DD
V
IN
= 0V
V
IN
= V
DD
V
IN
= 0V
At Output Disable, V
IN
= V
DD
At Output Disable, V
IN
= 0V
I
OH
= –2mA
I
OL
= +2mA
I
OH
= –4mA
I
OL
= +4mA
f
S
= 44.1kHz, SCLK = 384f
S
f
S
= 96kHz, SCLK = 256f
S
f
S
= 192kHz, SCLK = 128f
S
f
S
= 44.1kHz
f
S
= 96kHz
f
S
= 192kHz
EIAJ, A-Weighted, f
S
=44.1kHz
A-Weighted, f
S
= 96kHz
A-Weighted, f
S
=192kHz
EIAJ, A-Weighted, f
S
=44.1kHz
A-Weighted, f
S
= 96kHz
A-Weighted, f
S
= 192kHz
f
S
= 44.1kHz
f
S
= 96kHz
f
S
= 192kHz
2.4
1.0
2.4
1.0
0.0015
0.0020
0.0025
0.6
0.7
0.8
106
105
104
105
104
104
102
101
102
±1.0
±1.0
±30
62% of V
CC
50% V
CC
5
0.0035
0.0050
0.0060
0.8
1.0
1.2
0.1
–0.1
100
–0.1
2.0
–0.1
V
V
µA
µA
µA
µA
µA
µA
V
V
V
V
%
%
%
%
%
%
dB
dB
dB
dB
dB
dB
dB
dB
dB
% of FSR
% of FSR
mV
Vp-p
V
kΩ
MAX
UNITS
Bits
kHz
65
V
OUT
= –60dB
Dynamic Range
Signal-to-Noise Ratio
(5)
Channel Separation
102
100
98
100
100
100
96
96
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
DIGITAL FILTER PERFORMANCE
Filter Characteristic, Sharp Roll-Off
Passband
Stopband
Passband Ripple
Stopband Attenuation
Filter Characteristics, Slow Roll-Off 1
Passband
Stopband
Passband Ripple
Stopband Attenuation
V
O
= 0.5V
CC
at Bipolar Zero
Full Scale (0dB)
AC Load
±3.0
±3.0
±60
±0.002dB
–3dB
0.546f
S
Stopband = 0.546f
S
Stopband = 0.567f
S
±0.002dB
–3dB
0.732f
S
Stopband = 0.732f
S
–82
–75
–82
0.454f
S
0.490f
S
±0.002
Hz
Hz
Hz
dB
dB
dB
Hz
Hz
Hz
dB
dB
0.274f
S
0.454f
S
±0.002
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
PCM1737
2
SPECIFICATIONS
(Cont.)
All specifications at +25°C, +V
CC
= +5V, +V
DD
= +3.3V, system clock = 384f
S
(f
S
= 44.1kHz) and 24-bit data, unless otherwise noted.
Digital Input Voltage ........................................................... –0.2V to +5.5V
Digital Output Voltage
(1)
........................................... –0.2V to (V
DD
+ 0.2V)
Input Current (except power supply) ...............................................
±10mA
Power Dissipation .......................................................................... 650mW
Operating Temperature Range ............................................. 0°C to +70°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR reflow, 10s) .......................................... +235°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
324
SPECIFIED
TEMPERATURE
RANGE
0°C to +70°C
PACKAGE
MARKING
PCM1737E
ORDERING
NUMBER
(1)
PCM1737E
PCM1737E/2K
TRANSPORT
MEDIA
Rails
Tape and Reel
PRODUCT
PCM1737E
PACKAGE
28-Lead SSOP
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “PCM1737E/2K” will get a single 2000-piece Tape and Reel.
®
3
PCM1737
BLOCK DIAGRAM
PCM1737
BCLK
LRCK
Audio
Serial
I/F
DAC
Output Amp and
Low-Pass Filter
V
OUT
L
V
COM
L
DATA
TEST1
TEST2
RSTB
ML
MC
MDI
MDO
Mode
Control
I/F
4x/8x
Oversampling
Digital Filter
with
Function
Controller
Enhanced
Multi-level
Delta-Sigma
Modulator
DAC
Output Amp and
Low-Pass Filter
V
OUT
R
V
COM
R
System Clock
System Clock
Manager
Power Supply
SCLK
Zero Detect
V
DD
V
SS
ZEROL
ZEROR
GNDA
GNDL
PIN CONFIGURATION
Top View
SSOP
PIN ASSIGNMENTS
PIN
1
2
3
4
NAME
LRCK
DATA
BCLK
CLKO
SCLK
V
SS
V
DD
TEST1
TEST2
V
CC
R
GNDR
V
COM
R
V
OUT
R
GNDA
V
CC
A
V
OUT
L
V
COM
L
GNDL
V
CC
L
NC
NC
RSTB
ZEROL
ZEROR
MDO
MDI
MC
ML
I/O
I
I
I
O
I
—
—
I
I
—
—
—
O
—
—
O
—
—
—
—
—
I
O
O
O
I
I
I
DESCRIPTION
Left/Right Word Clock
(1)
Data In for Left/Right Channels
(1)
Bit Clock
(1)
System Clock Output
System Clock Input
(1)
Digital Ground
Digital Supply, +3.3V.
Test Pin
(2)
. Must be connected to
ground (V
SS
).
Test Pin
(2)
. Must be connected to
ground (V
SS
).
Analog Supply for Right Channel, +5V
Analog Ground for Right Channel
Common for Right Channel
Analog Output for Right Channel
Analog Ground
Analog Supply, +5V
Analog Output for Left Channel
Common for Left Channel
Analog Ground for Left Channel
Analog Supply for Left Channel, +5V
Not Connected
Not Connected
Reset, Active Low
(2)
.
Zero Flag for Left Channel
Zero Flag for Right Channel
Mode Data Out
(3)
Mode Data In
(2)
Mode Clock
(2)
Mode Latch
(2)
LRCK
DATA
BCLK
CLKO
SCLK
V
SS
V
DD
TEST1
TEST2
V
CC
R
GNDR
V
COM
R
V
OUT
R
GNDA
1
2
3
4
5
6
7
PCM1737E
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ML
MC
MDI
MDO
ZEROR
5
6
7
8
9
10
ZEROL
RSTB
NC
NC
V
CC
L
GNDL
V
COM
L
V
OUT
L
V
CC
A
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NOTES: (1) Schmitt-Trigger input, 5V tolerant. (2) Schmitt-Trigger input with
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