PCM1606
SLES014B – OCTOBER 2001 – REVISED AUGUST 2002
24-BIT, 192-kHz SAMPLING, 6-CHANNEL, ENHANCED MULTILEVEL,
DELTA-SIGMA DIGITAL-TO-ANALOG CONVERTER
FEATURES
D
24-Bit Resolution
D
Analog Performance:
– Dynamic Range: 103 dB, Typical
– SNR: 103 dB, Typical
– THD+N: 0.004%, Typical
– Full-Scale Output: 3.1 Vp-p, Typical
8× Oversampling Interpolation Filter:
– Stopband Attenuation: –55 dB
– Passband Ripple:
±0.03
dB
Sampling Frequency:
– 5 kHz to 200 kHz (Channels 1 and 2)
– 5 kHz to 100 kHz (Channels 3, 4, 5, and 6)
Accepts 16- and 24-Bit Audio Data
Data Formats: Standard, I
2
S, and
Left-Justified, TDM
System Clock: 128 f
S
, 192 f
S
, 256 f
S
, 384 f
S
,
512 f
S
, or 768 f
S
Digital De-Emphasis for 32 kHz, 44.1 kHz,
48 kHz
Power Supply: 5-V Single Supply
20 -Lead SSOP Package
DESCRIPTION
The PCM1606 is a CMOS monolithic integrated circuit
that features six 24-bit audio digital-to-analog
converters and support circuitry in a small 20-lead
SSOP package. The digital-to-analog converters utilize
Texas Instruments’ enhanced multilevel, delta-sigma
architecture, which employs 2
nd
-order noise shaping
and 8-level amplitude quantization to achieve excellent
signal-to-noise performance and a high tolerance to
clock jitter.
The PCM1606 accepts industry-standard audio data
formats with 16- to 24-bit audio data. Sampling rates up
to 200 kHz are supported.
D
D
D
D
D
D
D
D
PCM1606
(TOP VIEW)
APPLICATIONS
D
Integrated A/V Receivers
D
DVD Movie and Audio Players
D
HDTV Receivers
D
Car Audio Systems
D
DVD Add-On Cards for High-End PCs
D
Digital Audio Workstations
D
Other Multichannel Audio Systems
DATA1
DATA2
DATA3
FMT1
FMT0
ZEROA
AGND
V
OUT
5
V
OUT
6
V
OUT
1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SCKI
BCK
LRCK
DEMP1
DEMP0
V
CC
V
COM
V
OUT
4
V
OUT
3
V
OUT
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
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1
PCM1606
SLES014B – OCTOBER 2001 – REVISED AUGUST 2002
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
ZZ334 1
ZZ334-1
OPERATION
TEMPERATURE
RANGE
25°C
–25°C to 85°C
PACKAGE
MARKING
PCM1606E
ORDERING
NUMBER†
PCM1606E
PCM1606E
20 Lead SSOP
20-Lead
TRANSPORT MEDIA
TUBE
PCM1606E/2K
Tape and Reel
† Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000
pieces of PCM1606Y/2K gets a single 2000-piece tape and reel.
functional block diagram
DAC
Serial
Input
I/F
4x / 8x
Oversampling
Output Amp and
Low-Pass Filter
Output Amp and
Low-Pass Filter
Output Amp and
Low-Pass Filter
Output Amp and
Low-Pass Filter
Output Amp and
Low-Pass Filter
Output Amp and
Low-Pass Filter
BCK
LRCK
DATA1(1, 2)
DATA2(3, 4)
DATA3(5, 6)
Enhanced
Multilevel
Delta-Sigma
Modulator
VOUT1
DAC
VOUT2
DAC
VOUT3
Digital Filter
with
Function
Controller
DEMP1
DEMP0
FMT1
FMT0
Function
Control
I/F
DAC
VCOM
VOUT4
DAC
VOUT5
DAC
System Clock
SCKI
System Clock
VOUT6
Manager
Zero Detect
Power Supply
ZEROA
VCC
AGND
2
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PCM1606
SLES014B – OCTOBER 2001 – REVISED AUGUST 2002
Terminal Functions
TERMINAL
NAME
AGND
BCK
DATA1
DATA2
DATA3
DEMP0
DEMP1
FMT1
FMT0
LRCK
SCKI
VCC
VCOM
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
ZEROA
PIN
7
19
1
2
3
16
17
4
5
18
20
15
14
10
11
12
13
8
9
6
I/O
—
I
I
I
I
I
I
I
I
I
I
—
—
O
O
O
O
O
O
O
Analog and digital ground
Shift clock input for serial audio data (see Note 2)
Serial audio data input for VOUT1 and VOUT2 (see Note 2)
Serial audio data input for VOUT3 and VOUT4 (see Note 2)
Serial audio data input for VOUT5 and VOUT6 (see Note 2)
De-emphasis control (see Note 1)
De-emphasis control (see Note 1)
Format select (see Note 1)
Format select (see Note 1)
Left and right clock input. This clock is equal to the sampling rate, fS (see Note 2)
System clock in. Input frequency is 128 fS, 192 fS, 256 fS, 384 fS, 512 fS or 768 fS (see Note 2)
Analog and digital power supply, 5 V
Common voltage output. This pin should be bypassed with a 10-µF capacitor to AGND
Voltage output for audio signal corresponding to L-channel on DATA1. Up to 192 kHz
Voltage output for audio signal corresponding to R-channel on DATA1. Up to 192 kHz
Voltage output for audio signal corresponding to L-channel on DATA2. Up to 96 kHz
Voltage output for audio signal corresponding to R-channel on DATA2. Up to 96 kHz
Voltage output for audio signal corresponding to L-channel on DATA3. Up to 96 kHz
Voltage output for audio signal corresponding to R-channel on DATA3. Up to 96 kHz
Zero-data flag. Logical AND of ZERO1 through ZERO6
DESCRIPTIONS
NOTES: 1. Schmitt-trigger input with internal pulldown.
2. Schmitt-trigger input.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 V
Digital input voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3
V to V
CC
+ 0.3 V
Analog input voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3
V to V
CC
+ 0.3 V
Input current (except power supply)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±10
mA
Ambient temperature under bias
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C
to 125°C
Storage temperature
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C
to 150°C
Junction temperature
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150°C
Lead temperature (soldering, 5s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5s
Package temperature (IR reflow, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10s
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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3
PCM1606
SLES014B – OCTOBER 2001 – REVISED AUGUST 2002
electrical characteristics, all specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 44.1 kHz,
system clock = 384 f
S
and 24-bit data (unless otherwise noted)
PCM1606E
PARAMETER
RESOLUTION
DATA FORMAT
Audio data interface format
Audio data bit length
Audio data format
fS
Sampling frequency
System clock frequency
DIGITAL INPUT/OUTPUT
Logic family (TTL compatible)
VIH
VIL
IIH
IIL
VOH
VOL
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
High-level output voltage
Low-level output voltage
VIN = VCC
VIN = 0 V
IOH = –4 mA
IOL = 4 mA
fS = 44.1 kHz/384 fS
fS = 96 kHz/256 fS
fS = 192 kHz/128 fS
fS = 44.1 kHz/348 fS
VOUT = –60 dB
60
fS = 96 kHz / 256 fS
fS = 192 kHz/128 fS
EIAJ, A-weighted, fS = 44.1 kHz/384 fS
Dynamic range
A-weighted, fS = 96 kHz/256 fS
A-weighted, fS = 192 kHz/128 fS
EIAJ, A-weighted, fS = 44.1 kHz/384 fS
Signal to noise
Signal-to-noise ratio
A-weighted, fS = 96 kHz/256 fS
A-weighted, fS = 192 kHz/128 fS
Channel se aration
separation
Level linearity error
DC ACCURACY
Gain error
Gain mismatch, channel-to-channel
Bipolar zero error
ANALOG OUTPUT
Output voltage
Center voltage
Load impedance
Ac load
5
Full scale (–0 dB)
62% of VCC
50% of VCC
Vp-p
Vdc
kΩ
VOUT = 0.5 VCC at BPZ
±1
%FSR
±1.3
%FSR
±30
mV
fS = 44.1 kHz/384 fS
fS = 96 kHz/256 fS
fS = 192 kHz/128 fS
VOUT = –90 dB
95
98
98
2.4
1
0.004%
0.005%
0.002%
1%
1.2%
1%
103
99
101
103
100
101
100
95
100
±0.5
dB
dB
dB
dB
0.01%
67
2
0.8
100
–10
V
V
µA
µA
V
V
VOUT1, VOUT2
VOUT3, VOUT4, VOUT5, VOUT6
Standard, I2S, Left-Justified, TDM
16 or 24 bits, selectable
MSB first, 2s complement
5
5
200
100
kHz
TEST CONDITIONS
MIN
TYP
24
MAX
UNIT
Bits
128, 192, 256, 384, 512, 768 fS
DYNAMIC PERFORMANCE
VOUT = 0 dB
THD+N
Total harmonic
distortion plus noise
4
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PCM1606
SLES014B – OCTOBER 2001 – REVISED AUGUST 2002
electrical characteristics, all specifications at T
A
= 25°C, V
CC
= 5 V, f
S
= 44.1 kHz,
system clock = 384 f
S
and 24-bit data (unless otherwise noted) (continued)
PCM1606E
PARAMETER
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS
Passband
Stopband
Passband ripple
Stopband attenuation
ANALOG FILTER PERFORMANCE
Frequency response
POWER SUPPLY REQUIREMENTS (see Note 4)
VCC
ICC
Voltage range
fS = 44.1 kHz/384 fS
fS = 96 kHz/256 fS
fS = 192 kHz/128 fS
fS = 44.1 kHz/384 fS
Power dissi ation
dissipation
TEMPERATURE RANGE
Operation temperature
–25
85
°C
θ
JA
Thermal resistance
20-pin SSOP
115
°C/W
NOTES: 3. Analog performance specs are tested using System Two Cascade Plus by Audio Precision with 400-Hz HPF, 30-kHz LPF on at RMS
with 20-kHz LPF, 400-Hz HPF in calculation.
Shibasoku #725 THD meter, 400 Hz HPF, 30 kHz LPF on, at average mode with 20-kHz bandwidth limiting. The load connected
to the analog output is 5 kΩ or larger via capacitance coupling.
4. Condition in 192-kHz operation is channel 3 through channel 6 are disabled.
fS = 96 kHz/256 fS
fS = 192 kHz/128 fS
4.5
5
50
72
68
250
360
340
358
mW
5.5
65
mA
VDC
At 20 kHz
–0.03
dB
Stopband = 0.546 fS
Stopband = 0.567 fS
–50
–55
dB
±0.03
dB
–3 dB
0.546 fS
±0.03
dB
0.454 fS
0.487 fS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply current
Su ly
timing requirements
system clock input
The PCM1606 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma
modulators. The system clock is applied at the SCKI (pin 20). Table 1 shows examples of system clock
frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multiclock generator is an
excellent choice for providing the PCM1606 system clock source.
The 192-kHz sampling frequency operation is available on DATA1 for V
OUT
1 and V
OUT
2. When the system clock
of 128 f
S
or 192 f
S
is detected, V
OUT
3, V
OUT
4, V
OUT
5 and V
OUT
6 are automatically forced to the bipolar zero
level (= 0.5 V
CC
). Table 1 lists the typical system clock frequency.
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