INTEGRATED CIRCUITS
PCKV857
70–190 MHz differential 1:10 clock driver
Product data
Supersedes data of 2001 Mar 16
File under Intergrated Circuits ICL03
2001 Jun 12
Philips
Semiconductors
Philips Semiconductors
Product data
70–190 MHz differential 1:10 clock driver
PCKV857
FEATURES
•
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
PIN CONFIGURATION
GND 1
Y
0
2
Y
0
3
V
DDQ
4
Y
1
5
Y
1
6
GND 7
GND 8
Y
2
9
Y
2
10
V
DDQ
11
V
DDQ
12
CLK 13
CLK 14
V
DDQ
15
AV
DD
16
AGND 17
GND 18
Y
3
19
Y
3
20
V
DDQ
21
Y
4
22
Y
4
23
GND 24
48 GND
47 Y
5
46 Y
5
45 V
DDQ
44 Y
6
43 Y
6
42 GND
41 GND
40 Y
7
39 Y
7
38 V
DDQ
37 PWRDWN
36 FB
IN
35 FB
IN
34 V
DDQ
33 FB
OUT
32 FB
OUT
31 GND
30 Y
8
29 Y
8
28 V
DDQ
27 Y
9
26 Y
9
25 GND
•
Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
•
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications as per JEDEC specifications
•
1-to-10 differential clock distribution
•
Very low skew (< 100 ps) and jitter (< 100 ps)
•
Operation from 2.2 V to 2.7 V AV
DD
and 2.3 V to 2.7 V V
DD
•
SSTL_2 interface clock inputs and outputs
•
CMOS control signal input
•
Test mode enables buffers while disabling PLL
•
Low current power-down mode
•
Tolerant of Spread Spectrum input clock
•
Full DDR solution provided when used with SSTL16877 or
SSTV16857
•
See PCKV856 for I
2
C capable clock driver
DESCRIPTION
The PCKV857 is a high-performance, low-skew, low-jitter zero delay
buffer designed for 2.5 V V
DD
and 2.5 V AV
DD
operation and
differential data input and output levels.
The PCKV857 is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to ten differential pairs of clock outputs
(Y[0:9], Y[0:9]) and one differential pair feedback clock outputs
(FB
OUT
, FB
OUT
) . The clock outputs are controlled by the clock
inputs (CLK, CLK), the feedback clocks (FB
IN
, FB
IN
), and the analog
power input (AV
DD
). When PWRDWN is high, the outputs switch in
phase and frequency with CLK. When PWRDWN is low, all outputs
are disabled to high impedance state (3-State), and the PLL is shut
down (low power mode). The device also enters the low power
mode when the input frequency falls below 20 MHz. An input
frequency detection circuit will detect the low frequency condition
and after applying a > 20 MHz input signal, the detection circuit
turns on the PLL again and enables the outputs.
When AV
DD
is grounded, the PLL is turned off and bypassed for test
purposes. The PCKV857 is also able to track spread spectrum
clocking for reduced EMI.
The PCKV857 is characterized for operation from 0 to +70
°C.
SW00691
ORDERING INFORMATION
PACKAGES
48-Pin Plastic TSSOP
TEMPERATURE RANGE
0 to +70
°C
ORDER CODE
PCKV857DGG
DRAWING NUMBER
SOT362-1
2001 Jun 12
2
853–2242 26485
Philips Semiconductors
Product data
70–190 MHz differential 1:10 clock driver
PCKV857
PIN DESCRIPTION
PINS
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29,
30, 32, 33, 39, 40, 43, 44, 46, 47
4, 11, 12, 15, 21, 28, 34, 38, 46
13, 14, 35, 36
16
17
37
SYMBOL
GND
Y
n
, Y
n
, FB
OUT
, FB
OUT
V
DDQ
CLK
IN
, CLK
IN
, FB
IN
, FB
IN
AV
DD
AGND
PWRDWN
DESCRIPTION
SSTL_2 ground pins
SSTL_2 differential outputs
SSTL_2 power pins
SSTL_2 differential inputs
Analog power
Analog ground
Power-down control input
FUNCTION TABLE
INPUTS
PWRDWN
L
L
H
H
X
2
CLK
L
H
L
H
<
20 MHz
CLK
H
L
H
L
<
20 MHz
Y
n
Z
Z
L
H
Z
Y
n
Z
Z
H
L
Z
OUTPUTS
FB
OUT
Z
1
Z
1
L
H
Z
1
FB
OUT
Z
1
Z
1
H
L
Z
1
PLL ON/OFF
OFF
OFF
ON
ON
OFF
NOTES:
H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
X = don’t care
1. Subject to change. May cause conflict with FB
IN
pins.
2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.
BLOCK DIAGRAM
37 – PWRDWN
3 – Y
0
2 – Y
0
5 – Y
1
6 – Y
1
10 – Y
2
9 – Y
2
20 – Y
3
19 – Y
3
22 – Y
4
13 – CLK
14 – CLK
PLL
36 – FB
IN
35 – FB
IN
16 – AV
DD
23 – Y
4
46 – Y
5
47 – Y
5
44 – Y
6
43 – Y
6
39 – Y
7
40 – Y
7
29 – Y
8
30 – Y
8
27 – Y
9
28 – Y
9
32 – FB
OUT
33 – FB
OUT
SW00692
2001 Jun 12
3
Philips Semiconductors
Product data
70–190 MHz differential 1:10 clock driver
PCKV857
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
DDQ
AV
DD
V
I
V
O
I
IK
I
OK
I
O
T
stg
PARAMETER
Supply voltage range
Supply voltage range
Input voltage range
Output voltage range
Input clamp current
Output clamp current
Continuous output current
Continuous current to GND or V
DDQ
Storage temperature range
see Notes 2 and 3
see Notes 2 and 3
V
I
< 0 or V
I
>V
DDQ
V
O
< 0 or V
O
>V
DDQ
V
O
= 0 to V
DDQ
CONDITION
LIMITS
MIN
0.5
0.5
–0.5
–0.5
—
—
—
—
–65
MAX
3.6
3.6
V
DDQ
+
0.5
V
DDQ
+
0.5
±50
±50
±50
±100
+150
UNIT
V
V
V
V
mA
mA
mA
mA
°C
NOTES:
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 3.6 V maximum.
RECOMMENDED OPERATING CONDITIONS
1
SYMBOL
V
DDQ
AV
DD
V
IL
PARAMETER
Supply voltage range
Supply voltage range
g
Low level input voltage
CLK, CLK,
FB
IN
, FB
IN
PWRDWN
V
IH
g
g
High level input voltage
DC input signal voltage
V
ID
V
OX
V
IX
I
OH
I
OL
SR
T
amb
DC differential input signal voltage
AC differential input signal voltage
Output differential cross-voltage
Input differential cross-voltage
High-level output current
Low-level output current
Input slew rate
Operating free-air temperature
CLK, FB
IN
CLK, FB
IN
CLK, CLK,
FB
IN
, FB
IN
PWRDWN
Note 2
Note 3
Note 3
Note 4
Note 4
CONDITION
LIMITS
MIN
2.3
2.2
—
−0.3
V
DDQ
/2
+
0.18
1.7
−0.3
0.36
0.7
V
DDQ
/2
−
0.2
V
DDQ
/2
−
0.2
—
—
1
0
TYP
—
—
—
—
—
—
—
—
—
V
DDQ
/2
—
—
—
—
—
MAX
2.7
2.7
V
DDQ
/2
−
0.18
0.7
—
V
DDQ
+
0.3
V
DDQ
V
DDQ
+
0.6
V
DDQ
+
0.6
V
DDQ
/2
+
0.2
V
DDQ
/2
+
0.2
−12
12
4
70
V
V
V
V
V
mA
mA
V/ns
°C
V
UNIT
V
V
V
NOTES:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and
VCP is the complementary input level.
4. Differential cross-point voltage is expected to track variations of V
CC
and is the voltage at which the differential signals must be crossing.
2001 Jun 12
4
Philips Semiconductors
Product data
70–190 MHz differential 1:10 clock driver
PCKV857
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
V
IK
V
O
OH
PARAMETER
Input voltage, all inputs
High-level
High level output voltage
TEST CONDITIONS
V
DDQ
= 2.3 V, I
I
= –18 mA
V
DDQ
= min to max, I
OH
= –1 mA
V
DDQ
= 2.3 V, I
OH
= –12 mA
V
DDQ
= min to max, I
OL
= 1 mA
V
DDQ
= 2.3 V, I
OL
= 12 mA
V
DDQ
= 2.7 V, V
I
= 0 V to 2.7 V
V
DDQ
= 2.7 V, V
O
= V
DDQ
or GND
CLK and CLK = 0 MHz,
PWRDWN = low;
Σ
of I
DD
and AI
DD
f
O
= 67 MHz to 190 MHz
f
O
= 67 MHz to 190 MHz
V
CC
= 2.5 V, V
I
= V
CC
or GND
MIN
—
V
DDQ
−
0.1
1.7
—
—
—
—
—
—
—
2
TYP
—
—
—
—
—
—
—
30
200
8
2.8
MAX
−1.2
—
—
0.1
0.6
±10
±10
100
300
10
3
UNIT
V
V
V
V
V
µA
µA
µA
mA
mA
pF
V
O
OL
I
I
I
OZ
I
DDPD
I
DD
AI
DD
C
I
Low-level
Low level output voltage
Input current
High-impedance-state output current
Power-down current on V
DDQ
+ AV
DD
Dynamic current on V
DDQ
Supply current on AV
DD
Input capacitance
NOTE:
1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs.
2. All typical values are at respective nominal V
DDQ
.
3. Differential cross-point voltage is expected to track variations of V
DDQ
and is the voltage at which the differential signals must be crossing.
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature.
SYMBOL
f
CK
Operating clock frequency
Input clock duty cycle
Stabilization time
1
PARAMETER
MIN
60
40
100
MAX
190
60
—
UNIT
MHz
%
µs
NOTE:
1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power-up.
2001 Jun 12
5
京公网安备 11010802033920号
EEWORLD
