Philips Semiconductors
Preliminary specification
66–150MHz Phase Locked Loop Differential 1:10
SDRAM Clock Driver
PCK857
FEATURES
•
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
PIN CONFIGURATION
GND 1
Y
0
2
Y
0
3
V
DDQ
4
Y
1
5
Y
1
6
GND 7
GND 8
Y
2
9
Y
2
10
V
DDQ
11
V
DDQ
12
CLK 13
CLK 14
V
DDQ
15
AV
CC
16
AGND 17
GND 18
Y
3
19
Y
3
20
V
DDQ
21
Y
4
22
Y
4
23
GND 24
48 GND
47 Y
5
46 Y
5
45 V
DDQ
44 Y
6
43 Y
6
42 GND
41 GND
40 Y
7
39 Y
7
38 V
DDQ
37 G
36 FBIN
35 FBIN
34 V
DDQ
33 FBOUT
32 FBOUT
31 GND
30 Y
8
29 Y
8
28 V
DDQ
27 Y
9
26 Y
9
25 GND
•
1-to-10 differential clock distribution
•
Very low skew (< 100ps) and jitter (< 100ps)
•
3V AV
CC
and 2.5V V
ddq
•
SSTL_2 interface clock inputs and outputs
•
CMOS control signal input
•
Test mode enables buffers while disabling PLL
•
Low current power-down mode
•
Tolerant of Spread Spectrum input clock
•
Full DDR solution provided when used with SSTL16857 and
CBT3857
DESCRIPTION
Zero delay buffer to distribute an SSTL differential clock input pair to
10 SSTL_2 differential output pairs. Outputs are slope controlled.
External feedback pin for synchronization of the outputs to the input.
A CMOS style Enable/Disable pin is provided for low power disable.
SW00358
ORDERING INFORMATION
PACKAGES
48-Pin Plastic TSSOP
TEMPERATURE RANGE
0°C to +70°C
OUTSIDE NORTH AMERICA
PCK857 DGG
NORTH AMERICA
PCK857 DGG
DRAWING NUMBER
SOT362-1
PINS
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29,
30, 32, 33, 39, 40, 43, 44, 46, 47
4, 11, 12, 15, 21, 28, 34
13, 14, 35, 36
16
17
37
SYMBOL
GND
Y
n
, Y
nb
, FB
OUT
, FB
OUTb
V
DDQ
CLK
IN
, CLK
INb
, FB
IN
, FB
INb
AV
CC
AGND
G
DESCRIPTION
SSTL_2 ground pins
SSTL_2 differential outputs
SSTL_2 power pins
SSTL_2 differential inputs
Analog power
Analog ground
Power-down control input
1998 Dec 10
2
Philips Semiconductors
Preliminary specification
66–150MHz Phase Locked Loop Differential 1:10
SDRAM Clock Driver
PCK857
184/200-pin DDR SDRAM DIMM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
BACK SIDE
CBT
CBT
CBT
CBT
CBT
CBT
CBT
CBT
CBT
CBT3857 (9)
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE
SSTL16857
SSTL16857
PCK857
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SDRAM
SW00393
AC WAVEFORMS
skew
ANY TWO OUTPUTS
SW00396
Figure 1. Skew between any two outputs.
t
1
t
2
45%
v
t1
v
55%
t1
)
t2
SW00397
Figure 2. Duty cycle limits and measurement
1998 Dec 10
5
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