INTEGRATED CIRCUITS
PCK2020
CK00 (100/133MHz) spread spectrum
differential system clock generator
Product specification
Supersedes data of 2000 Jul 25
2000 Nov 13
Philips
Semiconductors
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
FEATURES
•
3.3 V operation
•
Four differential CPU clock pairs
•
Ten PCI clocks at 3.3 V
•
Four 66 MHz clocks at 3.3 V
•
Two 48 MHz clocks at 3.3 V
•
Two 14.318 MHz reference clocks
•
100 or 133 MHz operation
•
Power management control pins
•
CPU clock skew less than 200 ps cycle-to-cycle
•
CPU clock skew less than 150 ps pin-to-pin
•
1.5 ns to 3.5 ns delay on PCI pins
•
Spread Spectrum capability
DESCRIPTION
The PCK2020 is a clock synthesizer/driver for a Pentium III and
other similar processors.
The PCK2020 has four differential pair CPU current source outputs,
two Mref clock outputs running at 1/2 the CPU clock frequency
depending on the state of SEL133/100 pin and four 3V66 clocks
running at 66 MHz. There are ten PCI clock outputs running at
33 MHz and two 48 MHz clocks. Finally, there are two 3.3 V
reference clocks at 14.318 MHz. All clock outputs meet Intel’s drive
strength, rise/fall times, jitter, accuracy, and skew requirements.
The part possesses a dedicated power-down input pin for power
management control. This input is synchronized on-chip and
ensures glitch-free output transitions.
PIN CONFIGURATION
V
SS
Ref
Ref0/MultSel0
Ref1/MultSel1
V
DD
3.3Ref
XTAL_IN
XTAL_OUT
V
SS
PCI
PCICLK0
PCICLK1
1
2
3
4
5
6
7
8
9
56 V
DD
3.3M
55 3VMref
54 3VMref_b
53 V
SS
M
52 SPREAD
51 CPUCLK0
50 CPUCLK0
49 V
DD
3.3CPU
48 CPUCLK1
47 CPUCLK1
46 V
SS
CPU
45 CPUCLK2
44 CPUCLK2
43 V
DD
3.3CPU
42 CPUCLK3
41 CPUCLK3
40 V
SS
CPU
39 I_REF
38 V
DD
3.3Core
37 V
SS
Core
36 V
DD
3.3
35 3V66_0
34 3V66_1
33 V
SS
32 V
SS
31 3V66_2
30 3V66_3
29 V
DD
3.3
V
DD
3.3PCI 10
PCICLK2 11
PCICLK3 12
V
SS
PCI 13
PCICLK4 14
PCICLK5 15
V
DD
3.3PCI 16
PCICLK6 17
PCICLK7 18
V
SS
PCI 19
PCICLK8 20
PCICLK9 21
V
DD
3.3PCI 22
SEL100/133 23
V
SS
USB 24
48MHz0/SelA 25
48MHz1/SelB 26
V
DD
3.3USB 27
PWRDWN 28
SW00577
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP
TEMPERATURE RANGE (°C)
0 to +70
ORDER CODE
PCK2020 DL
DRAWING NUMBER
SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2000 Nov 13
2
853-2209 25006
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
PIN DESCRIPTION
PIN NUMBER
1
2, 3
4
5
6
7, 13, 19
8, 9, 11, 12, 14, 15, 17,
18, 20, 21
10, 16, 22
23
24
25, 26
27
28
29, 36
30, 31, 34, 35
32, 33
37
38
39
40, 46
41, 44, 47, 50
42, 45, 48, 51
43, 49
52
53
54
55
56
SYMBOL
V
SS
Ref
Ref0/MultSel0
Ref1/MultSel1
V
DD
3.3Ref
XTAL_IN
XTAL_OUT
V
SS
PCI
PCICLK[0–9]
V
DD
3.3PCI
SEL100/133
V
SS
USB
48 MHz/SelA
48 MHz/SelB
V
DD
3.3USB
PWRDWN
V
DD
3.3
3V66[0–3]
V
SS
V
SS
Core
V
DD
3.3Core
I_REF
V
SS
CPU
CPUCLK[0–3]
CPUCLK[0–3]
V
DD
3.3CPU
SPREAD
V
SS
M
3VMref_b
3VMref
V
DD
3.3M
3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending
on the state of input pin SEL133/100. (Out of phase with 3VMREF output).
3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending
on the state of input pin SEL133/100.
3.3 V power supply
Enables spread spectrum mode when held low on differential host outputs,
MREF/MREF_B clocks, 66 MHz clocks, and 33 MHz PCI clocks. Asserts low.
3.3 V power supply for analog circuits.
This pin controls the reference current for the host pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the correct current.
3.3 V fixed 66 MHz CPU clock outputs.
Device enters power down mode when held low. Asserts low.
3.3 V fixed 48 MHz clock outputs. During power up, pins functions as latched inputs
that enables SELA and SELB prior to the pins being used for output of 3 V at 48 MHz.
Part must be clocked to latch data in.
Select input pin for enabling 133 MHz or 100 MHz CPU outputs.
3.3 V PCI clock outputs fixed at 33 MHz.
Crystal input
Crystal output
During power up, pins functions as a latched inputs that enables MULTSEL0 and
MULTSEL1 prior to the pins being used for output of 3 V at 14.318 MHz. Part must be
clocked to latch data in.
FUNCTION
2000 Nov 13
3
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
BLOCK DIAGRAM
PWRDWN
X REF [0–1](14.318 MHz)
XIN X
14.318
MHZ
OSC
USBPLL
XOUT X
PWRDWN
X 48 MHz[0–1] 3 V
X CPUCLK [0–3]
SPREAD X
SYSPLL
PWRDWN
X CPUCLK [0–3]
SEL 133/100 X
SEL0 X
SEL1 X
DECODE
LOGIC
PWRDWN
X 3V66 [0–3] (66 MHz)
PWRDWN
X 3VMRef
PWRDWN
X PCICLK_F (33 MHz)
PWRDWN X
PWRDWN
X 3VMRef
PWRDWN
X PCICLK_F (33 MHz)
SW00727
2000 Nov 13
4
Philips Semiconductors
Product specification
CK00 (100/133MHz) spread spectrum
differential system clock generator
PCK2020
FUNCTION TABLES
SEL
100/133
0
0
0
0
1
1
1
1
SELA
0
0
1
1
0
0
1
1
SELB
0
1
0
1
0
1
0
1
HOST
100 MHz
105 MHz
1
200 MHz
HI-Z
133 MHz
126.7 MHz
1
200 MHz
TCLK/2
M
REF
50 MHz
52.5 MHz
1
50 MHz
HI-Z
66.7 MHz
63.3 MHz
1
66.7 MHz
TCLK/4
3V66
66.7 MHz
70 MHz
1
66.7 MHz
HI-Z
66.7 MHz
63.3 MHz
1
66.7 MHz
TCLK/4
3V33 PCI
33.3 MHz
35 MHz
1
33.3 MHz
HI-Z
33.3 MHz
31.7 MHz
1
33.3 MHz
TCLK/8
48 MHz
48 MHz
48 MHz
N/A
HI-Z
48 MHz
48 MHz
48 MHz
TCLK/2
REF
14.318 MHz
14.318 MHz
N/A
HI-Z
14.318 MHz
14.318 MHz
14.318 MHz
TCLK
NOTE:
1. These frequencies are for debug and thus can vary a small amount from the values listed at the vendor’s discretion.
SEL
100/133
0
0
0
0
1
1
1
1
SELA
0
0
1
1
0
0
1
1
SELB
0
1
0
1
0
1
0
1
Active 100 MHz
Active 100 MHz – ~5% over-clock
200 MHz, 50 MHz M
REF
HI-Z all outputs
Active 133 MHz
Active 133.3 MHz minus ~5 under-clock
200 MHz, 66 MHz M
REF
Test mode
HOST
POWER DOWN MODE
PWRDWN
Asserts low
0 = Active
HOST/HOST_BAR
HOST = 2*I
REF
HOST_BAR
MREF/MREF_B
LOW
3V66
LOW
PCI
LOW
48 MHz
LOW
REF
OFF
14.318/66 MHz Seeds
LOW/(if applicable)
NOTE:
1. The differential outputs should have a voltage forced across them when power down is asserted.
SPREAD SPECTRUM FUNCTION TABLE
SPREAD
1
0
FUNCTION
HOST/PCI/3V66/M
REF
/M
REF_B
No spread
HOST/PCI/3V66/M
REF
/M
REF_B
Down spread –0.5%
48 MHz PLL
REF/MULTSEL0
REF/MULTSEL1
No spread
No spread
2000 Nov 13
5
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