INTEGRATED CIRCUITS
PCK2011
Direct RAMbus Clock Generator
Preliminary specification
1999 Jan 19
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
Direct Rambus™ Clock Generator
PCK2011
Overview
The Direct Rambus Clock Generator (DRCG) provides the Channel
clock signals for a Direct Rambus memory subsystem. It includes
signals to synchronize the Direct Rambus Channel clock to an
external system clock. Contained in a 24-pin SSOP package, the
DRCG provides an off-the-shelf solution for a broad range of Direct
Rambus memory applications.
PIN CONFIGURATION
24 S0
23 S1
22 VDDO
21 GNDO
20 CLK
19 N/C
18 CLKB
17 GNDO
16 VDDO
15 MULT0
14 MULT1
13 S2
VDDLR
REFCLK
VDDP
GNDP
1
2
3
4
5
6
7
8
9
Features
GNDl
PCLKM
SYNCLKN
GNDC
VDDC
•
High Speed Clock Support
Provides a 400MHz differential clock source for Direct Rambus
memory systems for an 800MHz data transfer rate.
•
Synchronization Flexibility
The DRCG includes signals to synchronize the clock domains of
the RambusR Channel with an external system or processor
clock.
Power Management Support
The DRCG is able to turn off the Rambus Channel clock to
minimize power for mobile and other power-sensitive applications:
-
In the “clock off” mode, the DRCG remains on while the output
is disabled, allowing fast transitions between the clock-off and
clock-on states. This mode could be used in conjunction with
the Nap mode of the RDRAMs and Rambus ASIC Cell (RAC).
-
In the “power down” mode, the DRCG is completely powered
down for minimum power dissipation. This mode is used in
conjunction with the power down modes of the RDRAMs and
RAC.
VDDIPD 10
STOPB 11
PWRDNB 12
•
SW00289
Related Documentation
Direct Rambus RAC Overview
Direct Rambus Memory Controller Guide
Pin-outs
The DRCG is packaged in a 24-pin 150 mil SSOP. The pin
configuration shows the preliminary pin-out. Table 1 describes the
function and connection of each pin.
•
Supports Independent Channel Clocking
The DRCG supports systems that do not require synchronization
of the Rambus clock to another system clock.
Example System Clock Configuration
Figure 2 shows the clocking configuration for an example Direct
Rambus subsystem. The configuration shows the interconnection of
the system clock source, the Direct Rambus Clock Generator
(DRCG), and the clock signals of a memory controller ASIC. The
ASIC contains the RAC, the Rambus Memory Controller protocol
engine (RMC), and logic to support synchronizing the Channel clock
with the controller clock. (This diagram represents the differential
clocks as a single Busclk wire.)
•
Works with Philips PCK2010 to support Intel CK98 Clock
Synthesizer/Driver specification.
ORDERING INFORMATION
PACKAGES
24-Pin Plastic SSOP
TEMPERATURE RANGE
0°C to +70°C
OUTSIDE NORTH AMERICA
PCK2011 DL
NORTH AMERICA
PCK2011 DL
DRAWING NUMBER
SOT340-1
1999 Jan 19
2
Philips Semiconductors
Preliminary specification
Direct Rambus™ Clock Generator
PCK2011
Table 1. PIN DESCRIPTION
Pin
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
VDDLR
REFCLK
VDDP
GNDP
GNDl
PCLKM
SYNCLKN
GNDC
VDDC
VDDLPD
STOPB
PWRDnB
S2
MULT1
MULT0
VDDO
GNDO
CLKB
N/C
CLK
GNDO
VDDO
S1
S0
Type
RefV
In
Pwr
GND
GND
In
In
GND
Pwr
RefV
In
In
In
In
In
Pwr
GND
Out
N/C
Out
GND
Pwr
In
In
Function
Reference for REFCLK
Reference clock
VDD for PLL
GND for PLL
GND for control inputs
Phase Detector Input
Phase Detector Input
GND for Phase Aligner
VDD for Phase Aligner
Reference for P.D. Inputs
Active Low Output Disable
Active Low power down
Mode control input
PLL multiplier select
PLL multiplier select
VDD for clock outputs
GND for clock outputs
Output Clock (complement)
Not used
Output Clock
GND for clock outputs
VDD for clock outputs
Mode Control
Mode Control
Connect to CK133
Connect to CK133
3.3V Supply
Ground
Ground
Connect to Controller
Connect to Controller
Ground
3.3V Supply
Connect to Controller
Connect to Controller
3.3V CMOS
3.3V CMOS
3.3V CMOS
3.3V CMOS
3.3V Supply
Ground
Connect to Rambus Channel
Not connected (floating)
Connect to Rambus Channel
Ground
3.3V Supply
3.3V CMOS
3.3V CMOS
Notes
1999 Jan 19
3
Philips Semiconductors
Preliminary specification
Direct Rambus™ Clock Generator
PCK2011
This configuration achieves frequency-lock between the controller
and Rambus Channel clocks (PCLK and SYNCLK). These clock
signals are matched and phase-aligned at the RMC/RAC boundary
in order to allow data transfers to occur across this boundary without
additional latency.
The main clock source drives the system clock (PCLK) to the ASIC,
and also drives the reference clock (REFCLK) to the DRCG.
REFCLK may or may not be the same frequency as PCLK. A PLL
inside the DRCG multiplies REFCLK to generate the desired
frequency for BUSCLK. BUSCLK is driven on the Rambus Channel
through a terminated transmission line. At the mid-point of the
Channel, the RAC senses BUSCLK using its own DLL for clock
alignment, followed by a fixed divide-by- 4 circuit that generates
SYNCLK.
Pclk is the clock used in the Rambus memory controller (RMC) in
the ASIC. SYNCLK is the clock used at the ASIC interface of the
RAC. The DRCG together with the Gear Ratio Logic enables the
controller to exchange data directly from the PCLK domain to the
SYNCLK domain without incurring additional latency for
synchronization. In general, PCLK and SYNCLK can run at different
frequencies, so the Gear Ratio Logic must select the appropriate M
and N dividers such that the frequencies of PCLK/M and SYNCLK/N
are equal. In one example, PCLK=133MHz and SYNCLK=100MHz,
and M=4 while N=3, giving PCLK/M = SYNCLK/N = 33MHz. Figure
4 shows an example of the clock waveforms generated with the
Gear Ratio Logic.
PCK2010
REFCLK
Direct Rambus
Clock Generator
(DRCG)
BUSCLK
RDRAMs
SynClk/N
RMC
Pclk/M
RAC
PCLK
M
N
/4
SYNCLK
DLL
Gear Ratio-
Logic
CONTROLLER
SW00290
Figure 1. System Clock Architecture
The ASIC drives the output clocks, Pclk and SynClk/N from the
Gear Ratio Logic to the DRCG Phase Detector inputs. The routing
of the Pclk/M and SynClk/N signal traces must be matched in
impedance and propagation delay on the ASIC as well as on the
board. These signals are not part of the Rambus Channel and their
routing must be matched by board designers.
After comparing the phases of Pclk/M and SynClk/N, the DRCG
Phase Detector drives a phase aligner that adjusts the phase of
DRCG output clock, Busclk. Since the other elements in the
distributed loop have a fixed delay, adjusting Busclk adjusts the
phase of SynClk and thus the phase of SynClk/N.
In this manner, the distributed loop adjusts the phase of SynClk/N to
match that of Pclk/M, eliminating the phase error at the input of the
DRCG. When the clocks are aligned, data can be exchanged
directly from the Pclk domain to the SynClk domain.
The Gear Ratio Logic supports four clock ratios (2.0, 1.5, 1.33, and
1.0), where the ratio is defined as the ratio of Pclk/SynClk. Since
Busclk = 4*SynClk, this ratio also is equal to 4*Pclk/Busclk. Other
ratios could be used, depending on particular system
implementations.
1999 Jan 19
4
Philips Semiconductors
Preliminary specification
Direct Rambus™ Clock Generator
PCK2011
Power Management Modes
The DRCG device has three operating states: NORMAL, CLKSTOP
and POWERDOWN. In Normal mode, the clock source is on, and
the output is enabled. In CLKSTOP mode, the clock source is on,
but the output is disabled (STOPB deasserted). In Powerdown
mode, the device is powered down with the control signal PwrDnB
equal to 0. The control signals Mult0, Mult1, S0, S1 and S2 must be
stable before power is applied to the device, and can only be
changed in Power-down mode (PWRDNB=0).
Table 2. POWER MANAGEMENT MODES
MODE
NORMAL
CLKSTOP
POWERDOWN
PwrDnB
1
1
0
StopB
1
0
X
Clk
PACLK
V
X
, STOP
GND
ClkB
PACLKB
V
X
, STOP
GND
Upon applying power to the device, the device can enter any state,
depending on the settings of the control signals, PwrDnB and StopB.
The clock source output need not be glitch-free during state
transitions.
PWRDNB
S0
S1
S2
STOPB
DRCG
TEST MUX
BYPASS MUX
BYPCLK
PLLCLK
X
CLK
REFCLK
B
PPL
A
PHASE
ALIGNER
PACLK
CLKB
ΦD
MULT
0
MULT
1
2
PCLKM
SYNCLKN
SW00360
Figure 2. Direct Rambus Clock Generator Package
1999 Jan 19
5
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