INTEGRATED CIRCUITS
PCK2010
CK98 (100/133MHz) Spread Spectrum
System Clock Generator
Preliminary specification
1999 Mar 01
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
FEATURES
•
Mixed 2.5V and 3.3V operation
•
Four CPU clocks at 2.5V
•
Eight PCI clocks at 3.3V, one free-running
(synchronous with CPU clocks)
PIN CONFIGURATION
V
SS
REF0
REF1
VDD3V
XTAL_IN
XTAL_OUT
V
SS
PCICLK_F
PCICLK1
VDD3V
PCICLK2
PCICLK3
V
SS
PCICLK4
PCICLK5
VDD3V
PCICLK6
PCICLK7
V
SS
V
SS
3V66_0
3V66_1
VDD3V
V
SS
3V66_2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD25V
APIC2
APIC1
APIC0
V
SS
VDD25V
CPUDIV2_1
CPUDIV2_0
V
SS
VDD25V
CPUCLK3
CPUCLK2
V
SS
VDD25V
CPUCLK1
CPUCLK0
V
SS
VDD3V
V
SS
PCISTOP
CPUSTOP
PWRDWN
SPREAD
SEL1
SEL0
VDD3V
48MHz
V
SS
•
Four 3.3V fixed clocks @ 66MHz
•
Two 2.5V CPUDIV2 clocks @
½
CPU clock frequency
•
Three 2.5V IOAPIC clocks @ 16.67 MHz
•
One 3.3V 48MHz USB clock
•
Two 3.3V reference clocks @ 14.318 MHz
•
Reference 14.31818 MHz Xtal oscillator input
•
133 MHz or 100 MHz operation
•
Power management control input pins
•
LOW CPU clock jitter
≤
250 ps cycle-cycle
•
LOW skew outputs
•
0.0ns – 1.5ns CPU - 3V66 delay
•
1.5ns – 4.0ns 3V66 - PCI delay
•
1.5ns – 4.0 ns CPU - IOAPIC delay
•
Available in 56-pin SSOP package
•
±0.5%
center spread spectrum capability via select pins; –0.5%
down spread spectrum capability via select pins
DESCRIPTION
The PCK2010 is a clock synthesizer/driver chip for a PentiumII and
other similar processors.
The PCK2010 has four CPU clock outputs at 2.5V, two CPUDIV2
clock outputs running at
½
CPU clock frequency (66MHz or 50MHz
depending on the state of SEL133/100) and four 3V66 clocks
running at 66MHz. There are eight PCI clock outputs running at
33MHz. One of the PCI clock outputs is free-running. Additionally,
the part has three 2.5V IOAPIC clock outputs at 16.67MHz and two
3.3V reference clock outputs at 14.318MHz. All clock outputs meet
Intel’s drive strength, rise/fall time, jitter, accuracy, and skew
requirements.
The part possesses dedicated power-down, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs and
3V66 clock outputs are driven LOW. When the PCISTOP input is
asserted, the PCI clock outputs are driven LOW.
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
3V66_3
VDD3V
SEL133/100
SW00352
ORDERING INFORMATION
PACKAGES
56-Pin Plastic SSOP
TEMPERATURE RANGE
0°C to +70°C
OUTSIDE NORTH AMERICA
PCK2010 DL
NORTH AMERICA
PCK2010 DL
DRAWING NUMBER
SOT371-1
Intel and Pentium are registered trademarks of Intel Corporation.
2
1999 Mar 01
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
PIN DESCRIPTION
PIN NUMBER
2,3
5
6
8
9, 11, 12, 14, 15, 17, 18
21, 22, 25, 26
28
30
32, 33
34
35
36
37
41, 42, 45, 46
49, 50
53, 54, 55
4, 10, 16, 23, 27, 31, 39
1, 7, 13, 19, 20, 24, 29, 38, 40, 44,
48, 52
43, 47, 51, 56
SYMBOL
REF [0–1]
XTAL_IN
XTAL_OUT
PCICLK_F
PCICLK [1–7]
3V66 [0–3]
SEL133/100
48MHz
SEL [0–1]
SPREAD
PWRDWN
CPUSTOP
PCISTOP
CPUCLK [0–3]
CPUDIV_2 [0–1]
IOAPIC [0–2]
V
DD3V
V
SS
V
DD25V
FUNCTION
3.3V 14.318 MHz clock output
14.318 MHz crystal input
14.318 MHz crystal output
3.3V free running PCI clock
3.3V PCI clock outputs
3.3V fixed 66MHz clock outputs
Select input pin for enabling 133MHz or 100MHz CPU outputs.
H = 133MHz, L = 100MHz
3.3V fixed 48MHZ clock output
Logic select pins. TTL levels.
3.3V LVTTL input. Enables spread spectrum mode when held
LOW.
3.3V LVTTL input. Device enters powerdown mode when held
LOW.
3.3V LVTTL input. Stops all CPU clocks and 3V66 clocks when
held LOW. CPUDIV_2 output remains on all the time.
3.3V LVTTL input. Stops all PCI clocks except PCICLK_F when
held LOW.
2.5V CPU output. 133MHz or 100MHz depending on state of input
pin SEL133/100.
2.5V output running at 1/2 CPU clock frequency. 66MHz or 50MHz
depending on state of input pin SEL133/100.
2.5V clock outputs running divide synchronous with the CPU clock
frequency. Fixed 16.67 MHz limit.
3.3V power supply.
Ground
2.5V power supply
NOTES:
1. V
DD3V
, V
DD25V
and V
SS
in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise
on the performance of the device. In reality, the platform will be configured with the V
DD25V
pins tied to a 2.5V supply, all remaining V
DD
pins
tied to a common 3.3V supply and all V
SS
pins being common.
1999 Mar 01
3
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
BLOCK DIAGRAM
LOGIC
PWRDWN
LOGIC
XTAL_IN X
14.318
MHZ
OSC
USBPLL
X REF [0–1](14.318 MHz)
XTAL_OUT X
PWRDWN
LOGIC
X 48MHz
SYSPLL
STOP
X CPUCLK [0–3]
STOP
LOGIC
X 3V66 [0–3] (66MHz)
PWRDWN
LOGIC
SEL0 X
SEL1 X
SPREAD X
SEL133/100 X
PCISTOP X
CPUSTOP X
STOP
PWRDWN
LOGIC
X CPUDIV2 [0–1]
X PCICLK_F (33MHz)
X PCICLK [1–7] (33MHz)
PWRDWN X
PWRDWN
LOGIC
X APIC [0–2] (½ PCI)
SW00353
1999 Mar 01
4
Philips Semiconductors
Preliminary specification
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
PCK2010
168-pin SDR SDRAM DIMM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE
AVC
AVC
AVC
PCK2509S or PCK2510S
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SDRAM
SW00403
FUNCTION TABLE
SEL
133/100
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
HI-Z
N/A
100MHz
100MHz
TCLK/2
N/A
133MHz
133MHz
CPUDIV2
HI-Z
N/A
50MHz
50MHz
TCLK/4
N/A
66MHz
66MHz
3V66
HI-Z
N/A
66MHz
66MHz
TCLK/4
N/A
66MHz
66MHz
PCI
HI-Z
N/A
33MHz
33MHz
TCLK/8
N/A
33MHz
33MHz
48MHz
HI-Z
N/A
HI-Z
48MHz
TCLK/2
N/A
HI-Z
48MHz
REF
HI-Z
N/A
14.318MHz
14.318MHz
TCLK
N/A
14.318MHz
14.318MHz
IOAPIC
HI-Z
N/A
16.67MHz
16.67MHz
TCLK/16
N/A
16.67MHz
16.67MHz
NOTES
1
2
3
4, 7, 8
5, 6
2
3
4, 7, 8
NOTES:
1. Required for board level ‘‘bed-of-nails” testing.
2. Used to support Intel confidential application.
3. 48MHz PLL disabled to reduce component jitter. 48MHz outputs to be held Hi-Z instead of driven to LOW state.
4. ‘‘Normal” mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316MHz, NOMINAL = 14.31818MHz, MAX = 14.32MHz
CLOCK OUTPUT
USBCLK
7
TARGET FREQUENCY (MHz)
48.0
ACTUAL FREQUENCY (MHz)
48.008
PPM
167
1999 Mar 01
5
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