INTEGRATED CIRCUITS
PCK2002M
0–300 MHz I
2
C 1:10 clock buffer
Product data
File under Integrated Circuits ICL03
2001 Jul 19
Philips
Semiconductors
Philips Semiconductors
Product data
0–300 MHz I
2
C 1:10 clock buffer
PCK2002M
FEATURES
•
HIGH speed, LOW noise non-inverting 1:10 buffer
•
Mobile (reduced pincount) version of PCK2002
•
Typically used to support two SDRAM DIMMs
•
28-pin SSOP and TSSOP packages
•
See PCK2002 for 48-pin 1-18 buffer part supporting up to
4 SDRAM DIMMs
DESCRIPTION
The PCK2002M is a 1–10 fanout buffer used for 133/100 MHz CPU,
66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM
clock distribution. 10 outputs are typically used to support up to
2 SDRAM DIMMs commonly found in laptop or mobile applications.
The PCK2002M has the same features and operating characteristics
of the PCK2002 and is available in the SSOP 28 pin package.
All clock outputs meet Intel’s drive, rise/fall time, accuracy, and skew
requirements. An I
2
C interface is included to allow each output to be
enabled/disabled individually. An output disabled via the I
2
C
interface will be held in the LOW state. In addition, there is an OE
input which 3-states all outputs.
•
Optimized for 66 MHz, 100 MHz and 133 MHz operation
•
Multiple V
DD
and V
SS
pins for noise reduction
•
Spread spectrum compliant
•
175 ps skew outputs
•
Individual clock output enable/disable via I
2
C
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
t
r
t
f
I
CC
PARAMETER
Propagation delay
BUF_IN to BUF_OUT
n
Rise time
Fall time
Total supply current
CONDITIONS
V
CC
= 3.3 V, CL = 30 pF
V
CC
= 3.3 V, CL = 30 pF
V
CC
= 3.3 V, CL = 30 pF
V
CC
= 3.465 V
TYPICAL
2.7
2.9
1.1
1.0
35
UNIT
ns
ns
ns
µA
ORDERING INFORMATION
PACKAGES
28-Pin Plastic SSOP
28-Pin Plastic TSSOP
TEMPERATURE RANGE
0 to +70
°C
0 to +70
°C
ORDER CODE
PCK2002MDB
PCK2002MPW
DRAWING NUMBER
SOT341–1
SOT361–1
PIN CONFIGURATION
V
DD0
BUF_OUT0
BUF_OUT1
V
SS0
V
DD1
BUF_OUT2
BUF_OUT3
V
SS1
BUF_IN
1
2
3
4
5
28
27
26
25
24
V
DD9
BUF_OUT15
BUF_OUT14
V
SS9
V
DD8
BUF_OUT13
BUF_OUT12
V
SS8
OE
V
DD5
BUF_OUT17
V
SS5
V
SSI2C
SCL
PIN DESCRIPTION
PIN
NUMBER
2, 3, 6, 7
22, 23, 26,
27
11, 18
9
20
14
15
1, 5, 10,
19, 24, 28
4, 8, 12,
17, 21, 25
13
16
I/O
TYPE
Output
Output
Output
Input
Input
I/O
Input
Input
Input
Input
Input
SYMBOL
BUF_OUT
(0–3)
BUF_OUT
(12–15)
BUF_OUT
(16–17)
BUF_IN
OE
SDA
SCL
V
DD (0, 1, 4, 5, 8, 9)
V
SS (0, 1, 4, 5, 8, 9)
V
DDI2C
V
DDI2C
FUNCTION
Buffered clock outputs
Buffered clock outputs
Buffered clock outputs
Buffered clock input
Active high output
enable
I
2
C serial data
I
2
C serial clock
3.3 V power supply
Ground
3.3 V I
2
C power supply
I
2
C ground
6
7
8
9
PCK2002M
TOP VIEW
23
22
21
20
19
18
17
16
15
V
DD4
10
BUF_OUT16 11
V
SS4
12
V
DDI2C
13
SDA 14
SA00550
Intel and Pentium are registered trademarks of Intel Corporation.
I
2
C is a trademark of Philips Semiconductors Corporation.
2001 Jul 19
2
853-2268 26745
Philips Semiconductors
Product data
0–300 MHz I
2
C 1:10 clock buffer
PCK2002M
FUNCTION TABLE
OE
L
H
H
H
BUF_IN
X
L
H
H
I
2
CEN
X
X
H
L
BUF_OUTn
Z
L
H
L
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to V
SS
(V
SS
= 0 V)
SYMBOL
V
DD
I
IK
V
I
I
OK
V
O
I
O
T
stg
P
TOT
PARAMETER
DC 3.3 V supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
Storage temperature range
Power dissipation per package
plastic medium-shrink SO (SSOP)
For temperature range: 0 to +70
°C
above +55
°C
derate linearly with 11.3 mW/K
V
I
< 0
Note 2
V
O
> V
DD
or V
O
< 0
Note 2
V
O
≥
0 to V
DD
CONDITION
LIMITS
MIN
–0.5
—
–0.5
—
–0.5
—
–65
—
MAX
+4.6
–50
4.6
±50
V
CC
+ 0.5
±50
+150
850
UNIT
V
mA
V
mA
V
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
C
L
V
I
V
O
T
amb
PARAMETER
DC 3.3 V supply voltage
Capacitive load
DC input voltage range
DC output voltage range
Operating ambient temperature range in free air
CONDITIONS
LIMITS
MIN
3.135
20
0
0
0
MAX
3.465
30
V
DD
V
DD
+70
UNIT
V
pF
V
V
°C
2001 Jul 19
3
Philips Semiconductors
Product data
0–300 MHz I
2
C 1:10 clock buffer
PCK2002M
DC CHARACTERISTICS
SYMBOL
V
IH
V
IL
V
O
OH
V
O
OL
I
O
OH
I
O
OL
±I
I
±I
OZ
I
CC
∆I
CC
PARAMETER
V
DD
HIGH level input voltage
LOW level input voltage
3 3 V output HIGH voltage
3.3
3.3
3 3 V output LOW voltage
Output HIGH current
Output LOW current
Input leakage current
3-State output OFF-State
current
Quiescent supply current
Additional quiescent supply
current given per control pin
(V)
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135
3.135 to 3.465
3.135
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.465
3.465
3.465
3.135 to 3.465
V
OUT
= V
DD
or GND
V
I
= V
DD
or GND
V
I
= V
DD
– 0.6 V
I
O
= 0
I
O
= 0
I
O
= 0
I
OH
= –1 mA
I
OH
= –36 mA
I
OL
= 1 mA
I
OL
= 24 mA
V
OUT
= 2.0 V
V
OUT
= 3.135 V
V
OUT
= 1.0 V
V
OUT
= 0.4 V
TEST CONDITIONS
OTHER
LIMITS
T
amb
= 0 to +70
°C
MIN
2.0
V
SS
– 0.3
V
CC
– 0.1
2.4
—
—
–54
–21
49
24
—
—
—
—
MAX
V
DD
+ 0.3
0.8
—
—
0.1
0.4
–126
–46
118
53
±5
±10
100
500
V
V
V
V
mA
mA
µA
µA
µA
µA
UNIT
2001 Jul 19
4
Philips Semiconductors
Product data
0–300 MHz I
2
C 1:10 clock buffer
PCK2002M
AC CHARACTERISTICS
SYMBOL
T
SDRISE
T
SDFALL
T
PLH
T
PHL
T
PZL
, T
PZH
T
PLZ
, T
PHZ
DUTY CYCLE
T
SDSKW
T
DDSKW
PARAMETER
SDRAM rise time
SDRAM fall time
SDRAM buffer LH propagation delay
SDRAM buffer HL propagation delay
SDRAM buffer enable time
SDRAM buffer disable time
Output Duty Cycle
SDRAM Bus CLK skew
Device to device skew
Measured at 1.5 V
TEST CONDITIONS
NOTES
2, 4
2, 4
4, 5
4, 5
4, 5
4, 5
3, 4, 5
1, 4
MIN
1.5
1.5
1.2
1.2
1.0
1.0
45
—
—
LIMITS
T
amb
= 0°C to +70°C
TYP
7
2.0
2.9
2.7
2.7
2.6
2.7
52
150
—
MAX
4.0
4.0
3.5
3.5
5.0
5.0
55
250
500
V/ns
V/ns
ns
ns
ns
ns
%
ps
ps
UNIT
NOTES:
1. Skew is measured on the rising edge at 1.5 V.
2. T
SDRISE
and T
SDFALL
are measured as a transition through the threshold region V
OL
= 0.4 V and V
OH
= 2.4 V (1 mA) JEDEC specification.
3. Duty cycle should be tested with a 50/50% input.
4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.
5. Input edge rate for these tests must be faster than 1 V/ns.
6. Calculated at minimum edge rate (1.5 ns) to guarantee 45/55% duty cycle at 1.5 V. Pulsewidth is required to be wider at the faster edge to
ensure duty cycle specification is met.
7. All typical values are at V
CC
= 3.3 V and T
amb
= 25
°C.
8. Typical is measured with MAX (30 pF) discrete load.
9. Typical is measured with MIN (20 pF) discrete load.
2001 Jul 19
5
Embedded System
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