INTEGRATED CIRCUITS
PCK2002
0–300 MHz I
2
C 1:18 clock buffer
Product data
File under Integrated Circuits ICL03
2001 Jul 19
Philips
Semiconductors
Philips Semiconductors
Product data
0–300 MHz I
2
C 1:18 clock buffer
PCK2002
FEATURES
•
HIGH speed, LOW noise non-inverting 1–18 buffer
•
Typically used to support four SDRAM DIMMs
•
Multiple V
DD
, V
SS
pins for noise reduction
•
3.3 V operation
•
Separate 3-State pin for testing
•
ESD protection exceeds 2000 V per Standard 801.2
•
Optimized for 66 MHz, 100 MHz and 133 MHz operation
•
Typical 175 ps skew outputs
•
Available in 48-pin SSOP and TSSOP packages
•
See PCK2002M for mobile (reduced pincount) 28-pin 1-10 buffer
version
•
Spread spectrum compliant
•
Individual clock output enable/disable via I
2
C
DESCRIPTION
The PCK2002 is a 1–18 fanout buffer used for 133/100 MHz CPU,
66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM
clock distribution. 18 outputs are typically used to support up to
4 SDRAM DIMMS commonly found in desktop, workstation or
server applications.
All clock outputs meet Intel’s drive, rise/fall time, accuracy, and skew
requirements. An I
2
C interface is included to allow each output to be
enabled/disabled individually. An output disabled via the I
2
C
interface will be held in the LOW state. In addition, there is an OE
input which 3-States all outputs.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
t
r
t
f
I
CC
PARAMETER
Propagation delay
BUF_IN to BUF_OUT
n
Rise time
Fall time
Total supply current
CONDITIONS
V
CC
= 3.3 V, CL = 30 pF
V
CC
= 3.3 V, CL = 30 pF
V
CC
= 3.3 V, CL = 30 pF
V
CC
= 3.465 V
TYPICAL
2.7
2.9
1.1
1.0
35
UNIT
ns
ns
ns
µA
ORDERING INFORMATION
PACKAGES
48-Pin Plastic TSSOP
48-Pin Plastic SSOP
TEMPERATURE RANGE
0 to +70
°C
0 to +70
°C
ORDER CODE
PCK2002DGG
PCK2002DL
DRAWING NUMBER
SOT362-1
SOT370-1
PIN CONFIGURATION
RESERVED 1
RESERVED 2
V
DD0
3
BUF_OUT0 4
BUF_OUT1 5
V
SS0
6
V
DD1
7
BUF_OUT2 8
BUF_OUT3 9
V
SS1
10
V
DD2
12
BUF_OUT4 13
BUF_OUT5 14
V
SS2
15
V
DD3
16
BUF_OUT6 17
BUF_OUT7 18
V
SS3
19
V
DD4
20
BUF_OUT16 21
V
SS4
22
V
DDI2C
23
SDA 24
48 RESERVED
47 RESERVED
46 V
DD9
45 BUF_OUT15
44 BUF_OUT14
43 V
SS9
42 V
DD8
41 BUF_OUT13
40 BUF_OUT12
39 V
SS8
38 OE
PIN DESCRIPTION
PIN
NUMBER
4, 5, 8, 9
13, 14, 17, 18
31, 32, 35,
36
40, 41, 44,
45
21, 28
11
38
24
25
3, 7, 12, 16,
20, 29, 33,
37, 42, 46
6, 10, 15,
19, 22,
27, 30, 34,
39, 43
23
26
1, 2, 47, 48
2
I/O
TYPE
Output
Output
Output
Output
Output
Input
Input
I/O
Input
Input
SYMBOL
BUF_OUT (0–3)
BUF_OUT (4–7)
BUF_OUT
(8–11)
BUF_OUT
(12–15)
BUF_OUT
(16–17)
BUF_IN
OE
SDA
SCL
V
DD (0–9)
FUNCTION
Buffered clock outputs
Buffered clock outputs
Buffered clock outputs
Buffered clock outputs
Buffered clock outputs
Buffered clock input
Active high output
enable
I
2
C serial data
I
2
C serial clock
3.3 V Power supply
PCK2002
BUF_IN 11
37 V
DD7
36 BUF_OUT11
35 BUF_OUT10
34 V
SS7
33 V
DD6
32 BUF_OUT9
31 BUF_OUT8
30 V
SS6
29 V
DD5
28 BUF_OUT17
27 V
SS5
26 V
SSI2C
25 SCL
Input
V
SS (0–9)
Ground
3.3 V I
2
C Power
supply
I
2
C Ground
Undefined
853-2267 26745
Input
Input
n/a
V
DDI2C
V
SSI2C
RESERVED
SW00731
I
2
C is a trademark of Philips Semiconductors Corporation.
2001 Jul 19
Philips Semiconductors
Product data
0–300 MHz I
2
C 1:18 clock buffer
PCK2002
FUNCTION TABLE
OE
L
H
H
H
BUF_IN
X
L
H
H
I
2
CEN
X
X
H
L
BUF_OUTn
Z
L
H
L
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to V
SS
(V
SS
= 0V)
SYMBOL
V
DD
I
IK
V
I
I
OK
V
O
I
O
T
STG
P
TOT
PARAMETER
DC 3.3 V supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
Storage temperature range
Power dissipation per package
plastic medium-shrink SO (SSOP)
For temperature range: 0 to +70°C
above +55°C derate linearly with 11.3mW/K
V
I
< 0
Note 2
V
O
> V
DD
or V
O
< 0
Note 2
V
O
>= 0 to V
DD
–65
–0.5
–0.5
CONDITION
LIMITS
MIN
–0.5
MAX
+4.6
–50
+4.6
±50
V
CC
+ 0.5
±50
+150
850
UNIT
V
mA
V
mA
V
mA
°C
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
C
L
V
I
V
O
T
amb
PARAMETER
DC 3.3 V supply voltage
Capacitive load
DC input voltage range
DC output voltage range
Operating ambient temperature range in free air
CONDITIONS
LIMITS
MIN
3.135
20
0
0
0
MAX
3.465
30
V
DD
V
DD
+70
UNIT
V
pF
V
V
°C
2001 Jul 19
3
Philips Semiconductors
Product data
0–300 MHz I
2
C 1:18 clock buffer
PCK2002
DC CHARACTERISTICS
SYMBOL
V
IH
V
IL
V
O
OH
V
O
OL
I
O
OH
I
O
OL
±I
I
±I
OZ
I
CC
∆I
CC
PARAMETER
V
DD
HIGH level input voltage
LOW level input voltage
3 3V output HIGH voltage
3.3V
3.3V
3 3V output LOW voltage
Output HIGH current
Output LOW current
Input leakage current
3-State output OFF-State current
Quiescent supply current
Additional quiescent supply
current given per control pin
(V)
3.135 to 3.465
3.135 to 3.465
3.135 to 3.465
3.135
3.135 to 3.465
3.135
3.135
3.465
3.135 to 3.465
3.135 to 3.465
3.465
3.465
3.465
3.135 to 3.465
V
OUT
= V
DD
or GND
V
I
= V
DD
or GND
V
I
= V
DD
– 0.6V
I
O
= 0
I
O
= 0
I
O
= 0
I
OH
= –1 mA
I
OH
= –36 mA
I
OL
= 1 mA
I
OL
= 24 mA
V
OUT
= 2.0 V
V
OUT
= 3.135 V
V
OUT
= 1.0 V
V
OUT
= 0.4 V
TEST CONDITIONS
OTHER
LIMITS
T
amb
= 0 to +70
°C
MIN
2.0
V
SS
– 0.3
V
CC
– 0.1
2.4
—
—
–54
–21
49
24
—
—
—
—
MAX
V
DD
+ 0.3
0.8
—
—
0.1
0.4
–126
–46
118
53
±5
10
100
500
V
V
V
V
mA
mA
µA
µA
µA
µA
UNIT
AC CHARACTERISTICS
SYMBOL
T
SDRISE
T
SDFALL
T
PLH
T
PHL
T
PZL
, T
PZH
T
PLZ
, T
PHZ
DUTY CYCLE
T
SDSKW
T
DDSKW
PARAMETER
SDRAM rise time
SDRAM fall time
SDRAM buffer LH propagation delay
SDRAM buffer HL propagation delay
SDRAM buffer enable time
SDRAM buffer disable time
Output Duty Cycle
SDRAM Bus CLK skew
Device to device skew
Measured at 1.5 V
TEST CONDITIONS
NOTES
2, 4
2, 4
4, 5
4, 5
4, 5
4, 5
3, 4, 5
1, 4
MIN
1.5
1.5
1.2
1.2
1.0
1.0
45
—
—
LIMITS
T
amb
= 0 to +70
°C
TYP
6
2.0
2.9
2.7
2.9
2.6
2.7
52
150
—
MAX
4.0
4.0
3.5
3.5
5.0
5.0
55
250
500
V/ns
V/ns
ns
ns
ns
ns
%
ps
ps
UNIT
NOTES:
1. Skew is measured on the rising edge at 1.5 V.
2. T
SDRISE
and T
SDFALL
are measured as a transition through the threshold region V
OL
= 0.4 V and V
OH
= 2.4 V (1mA) JEDEC specification.
3. Duty cycle should be tested with a 50/50% input.
4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.
5. Input edge rate for these tests must be faster than 1 V/ns.
6. All typical values are at V
CC
= 3.3 V and T
amb
= 25
°C.
2001 Jul 19
4
Philips Semiconductors
Product data
0–300 MHz I
2
C 1:18 clock buffer
PCK2002
I
2
C CONSIDERATIONS
I
2
C has been chosen as the serial bus interface to control the PCK2002. I
2
C was chosen to support the JEDEC proposal JC-42.5 168 Pin
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I
2
C devices.
1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only
one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I
2
C clock driver is used in
the system.
The following address was confirmed by Philips on 09/04/96.
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
2
C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’
NOTE:
The R/W bit is used by the I
indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the
R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.
2) Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same address
as the original CKBF device. I
2
C addresses are defined in terms of function (master clock driver) rather than form (pinout, and option).
3) Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.
4) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.
5) Logic Levels: I
2
C logic levels are based on a percentage of V
DD
for the controller and other devices on the bus. Assume all devices are
based on a 3.3 Volt supply.
6) Data Byte Format: Byte format is 8 Bits as described in the following appendices.
7) Data Protocol: To simplify the clock I
2
C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I
2
C protocol.
The clock driver must meet this protocol which is more rigorous than previously stated I
2
C protocol. Treat the description from the viewpoint of
controller. The controller “writes” to the clock driver and if possible would “read” from the clock driver (the clock driver is a slave/receiver only
and is incapable of this transaction.)
“The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which
describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”
1 bit
Start bit
7 bits
Slave Address
1
R/W
1
Ack
8 bits
Command Code
1
Ack
Byte Count = N
Ack
1 bit
Data Byte 1
8 bits
Ack
1
Data Byte 2
8 bits
Ack
1
...
Data Byte 2
8 bits
Ack
1
Stop
1
SW00279
NOTE:
The acknowledgement bit is returned by the slave/receiver (the clock driver).
2001 Jul 19
5
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