Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
FEATURES
•
Mixed 2.5V and 3.3V operation
•
Four CPU clocks at 2.5V
•
Eight synchronous PCI clocks at 3.3V, one free-running
•
Two 2.5V IOAPIC clocks @ 14.318 MHz
•
Two 3.3V 48MHz USB clock outputs
•
Three 3.3V reference clocks @ 14.318 MHz
•
Reference 14.31818 MHz Xtal oscillator input
•
100 MHz or 66 MHz operation
•
Part provides frequencies for Pentium Pro and
Pentium II™ motherboards
PIN CONFIGURATION
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
REF0
REF1
V
SSREF
XTAL_IN
XTAL_OUT
V
SSPCI0
PCICLK_F
PCICLK1
V
DDREF
REF2
V
DDAPIC
IOAPIC0
IOAPIC1
V
SSAPIC
RESERVED
V
DDCPU0
CPUCLK0
CPUCLK1
V
SSCPU0
V
DDCPU1
CPUCLK2
CPUCLK3
V
SSCPU1
V
DDCORE1
V
SSCORE1
PCISTOP
CPUSTOP
PWRDWN
RESERVED
SEL0
SEL1
SEL100/66
V
DDPCI0
9
PCICLK2 10
PCICLK3 11
V
SSPCI1
12
PCICLK4 13
PCICLK5 14
V
DDPCI1
15
PCICLK6 16
PCICLK7 17
V
SSPCI2
18
•
Power management control input pins
•
175 ps CPU clock jitter
•
175 ps skew on outputs
•
1.5 – 4 ns CPU–PCI delay
•
Power down if PWRDWN is held LOW
•
Available in 48-pin SSOP package
•
See PCK2000M for 28-pin mobile version
DESCRIPTION
The PCK2000 is a clock synthesizer/driver chip for a Pentium Pro or
other similar processors.
The PCK2000 has four CPU clock outputs at 2.5V. There are eight
PCI clock outputs running at 33MHz. One of the PCI clock outputs is
free-running. Additionally, the part has two 3.3V USB clock outputs
at 48MHz, two 2.5V IOAPIC clock outputs at 14.318MHz, and three
3.3V reference clock outputs at 14.318MHz. All clock outputs meet
Intel’s drive strength, rise/fall time, jitter, accuracy, and skew
requirements.
The part possesses dedicated powerdown, CPUSTOP, and
PCISTOP input pins for power management control. These inputs
are synchronized on-chip and ensure glitch-free output transitions.
When the CPUSTOP input is asserted, the CPU clock outputs are
driven LOW. When the PCISTOP input is asserted, the PCI clock
outputs are driven LOW, except for free running PCICLK_F clock
output..
Finally, when the PWRDWN input pin is asserted, the internal
reference oscillator and PLLs are shut down, and all outputs are
driven LOW.
The PCK2000 is available in a 48–pin SSOP package.
PCK2000
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
DDCORE0
19
V
SSCORE0
20
V
DD
48MHz 21
48MHz0 22
48MHz1 23
V
SS
48MHz 24
SW00237
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP
TEMPERATURE RANGE
0°C to +70°C
OUTSIDE NORTH AMERICA
PCK2000 DL
NORTH AMERICA
PCK2000 DL
DRAWING NUMBER
SOT370-1
Intel and Pentium are registered trademarks of Intel Corporation.
1998 Sep 29
2
853-2129 20102
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
PIN DESCRIPTION
PIN NUMBER
1, 2, 47
3
48
4
5
6, 12, 18
7
9, 15
8, 10, 11, 13, 14, 16, 17
19, 33
20, 32
21
24
22, 23
26, 27
25
29
30
31
37, 41
34, 38
35, 36, 39, 40
43
46
44, 45
28, 42
SYMBOL
REF [0–2]
V
SSREF
V
DDREF
XTAL_IN
XTAL_OUT
V
SSPCI
[0–2]
PCICLK_F
V
DDPCI
[0–1]
PCICLK [1–7]
V
DDCORE
[0–1]
V
SSCORE
[0–1]
V
DD
48MHz
V
SS
48MHz
48MHz [0–1]
SEL0,1
SEL100/66
PWRDWN
CPUSTOP
PCISTOP
V
DDCPU
[0–1]
V
SSCPU
[0–1]
CPUCLK [0–3]
V
SSAPIC
V
DDAPIC
IOAPIC [0–1]
RESERVED
14.318 MHz clock outputs
GROUND for REF outputs
POWER for REF outputs
14.318 MHz crystal input
14.318 MHz crystal output
GROUND for PCI outputs
Free-running PCI output
POWER for PCI outputs
PCI clock outputs.
Isolated POWER for core
Isolated GROUND for core
POWER for 48MHz outputs
GROUND for 48MHz outputs
48MHz outputs
Logic select pins.
Select pin for enabling 66 MHz or 100MHz. L = 66 MHz
H = 100MHz
Control pin to put device in powerdown state, active low
Control pin to disable CPU clocks, active low
Control pin to disable PCI clocks, active low
POWER for CPU outputs
GROUND for CPU outputs
CPU clock outputs @2.5V
GROUND for IOAPIC outputs
POWER for IOAPIC outputs
IOAPIC output @ 2.5V
Reserved for future use
FUNCTION
NOTES:
1. V
DD
and V
SS
names in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise on
the performance of the device. In reality, the platform will be configured with the V
DDAPIC
and V
DDCPU
pins tied to a 2.5V supply, all
remaining V
DD
pins tied to a common 3.3V supply and all V
SS
pins being common.
1998 Sep 29
3
Philips Semiconductors
Product specification
CK97 (66/100MHz) System Clock Generator
PCK2000
FUNCTION TABLE
SEL 100/66
0
1
CPU/PCI RATIO
2
3
CPUCLK (0–3)
(MHz)
66.66
100
CPICLK (1–7)
PCICLK_F
(MHz)
33.33
33.33
REF (0–2)
IOAPIC (0–1)
(MHz)
14.318
14.318
48MHz (0–1)
48
48
CLOCK ENABLE CONFIGURATION
CPUSTOP
X
0
0
1
1
PCISTOP
X
0
1
0
1
PWRDWN
0
1
1
1
1
CPUCLK
LOW
LOW
LOW
100/66MHz
100/66MHz
PCICLK
LOW
LOW
33MHz
LOW
33MHz
PCICLK_F
LOW
33MHz
33MHz
33MHz
33MHz
OTHER
CLOCKS
Stopped
Running
Running
Running
Running
PLLs
OFF
Running
Running
Running
Running
OSCILLATOR
OFF
Running
Running
Running
Running
POWER MANAGEMENT REQUIREMENTS
LATENCY
SIGNAL
SIGNAL STATE
NO. OF RISING EDGES OF FREE RUNNING
PCICLK
1
1
1
1
3ms
2 MAX
CPUSTOP
0 (DISABLED)
1 (ENABLED)
PCISTOP
0 (DISABLED)
1 (ENABLED)
PWRDWN
1 (NORMAL OPERATION)
0 (POWER DOWN)
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
1998 Sep 29
5
京公网安备 11010802033920号
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