INTEGRATED CIRCUITS
PCK12429
25–400 MHz differential PECL
clock generator
Product data
Supersedes data of 2002 Mar 15
2002 Jun 03
Philips
Semiconductors
Philips Semiconductors
Product data
25–400 MHz differential PECL clock generator
PCK12429
INTRODUCTION
The PCK12429 is a general purpose synthesized clock source
targeting applications that require both serial and parallel interfaces.
The differential PECL output can be configured to be the VCO
frequency divided by 1, 2, 4, or 8. With the output configured to
divide the VCO frequency by 2, and with a 16.000 MHz external
quartz crystal used to provide the reference frequency, the output
frequency can be specified in 1 MHz steps. The PLL loop filter is
fully integrated so that no external components are required.
VCO control voltage. Note that for some values of M (either too high
or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider
before being sent to the PECL output driver. This output divider (N
divider) is configured through either the serial or the parallel
interfaces, and can provide one of four division ratios (1, 2, 4, or 8).
This divider extends performance of the part while providing a 50%
duty cycle.
The output driver is driven differentially from the output divider, and
is capable of driving a pair of transmission lines terminated in 50
Ω
to V
CC
–2.0. The positive reference for the output driver and the
internal logic is separated from the power supply for the
phase-locked loop to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The
parallel interface uses the values at the M[8:0] and N[1:0] inputs to
configure the internal counters. Normally, on system reset, the
P_LOAD input is held LOW until sometime after power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs
are captured. The parallel interface has priority over the serial
interface. Internal pullup resistors are provided on the M[8:0] and
N[1:0] inputs to reduce component count in the application of the
chip.
The serial interface centers on a fourteen bit shift register. The shift
register shifts once per rising edge of the S_CLOCK input. The
serial input S_DATA must meet setup and hold timing as specified in
the AC Characteristics section of this document. The configuration
latches will capture the value of the shift register on the
HIGH-to-LOW edge of the S_LOAD input. See the programming
section for more information.
The TEST output reflects various internal node values, and is
controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
FEATURES
•
25 to 400 MHz differential PECL outputs
•
±25
ps peak-to-peak output jitter
•
Fully integrated phase-locked loop
•
Minimal frequency over-shoot
•
Synthesized architecture
•
Serial 3-wire interface
•
Parallel interface for power-up
•
Quartz crystal interface
•
Package offer: SO28, PLCC28, and LQFP32
•
Operates from 3.3 V power supply
DESCRIPTION
The internal oscillator uses the external quartz crystal as the basis
of its frequency reference. The output of the reference oscillator is
divided by 16 before being sent to the phase detector.
The VCO output is scaled by a divider that is configured by either
the serial or parallel interfaces. The output of this loop divider is also
applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output
frequency to be M times the reference frequency by adjusting the
ORDERING INFORMATION
PACKAGES
28-Pin Plastic SO
28-Pin Plastic PLCC
32-pin Plastic LQFP
TEMPERATURE RANGE
0 to +70
°C
0 to +70
°C
0 to +70
°C
ORDER CODE
PCK12429D
PCK12429A
PCK12429BD
DRAWING NUMBER
SOT136-1
SOT261-2
SOT358-1
2002 Jun 03
2
853-2312 28362
Philips Semiconductors
Product data
25–400 MHz differential PECL clock generator
PCK12429
PIN CONFIGURATION
28-Pin SO
M[0] 1
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
M[8]
2
3
4
5
6
7
8
9
28 P_LOAD
27 V
CC
26 XTAL2
25 XTAL1
24 NC
23 NC
22 PLL-V
CC
21 S_LOAD
20 S_DATA
19 S_CLOCK
18 V
CC
17 FOUT
16 FOUT
15 GND
N[0] 10
N[1] 11
GND 12
TEST 13
V
CC
14
SW01013
28-Pin PLCC
PLL- V
CC
S_LOAD
S_CLOCK
26
25
24
23
TOP VIEW
22
21
20
19
12
M[4]
13
M[5]
14
M[6]
15
M[7]
16
M[8]
17
N[0]
18
N[1]
V
CC
FOUT
FOUT
GND
V
CC
TEST
GND
S_DATA
27
XTAL1
NC
NC
4
XTAL2 5
OE 6
P_LOAD 7
M[0]
8
3
2
28
M[1] 9
M[2] 10
M[3] 11
SR02303
2002 Jun 03
3
Philips Semiconductors
Product data
25–400 MHz differential PECL clock generator
PCK12429
32-Pin LQFP
31 FOUT
30 FOUT
26 TEST
20 GND
S_CLOCK
S_DATA
S_LOAD
PLL-V
CC
PLL-V
CC
N/C
N/C
XTAL1
25 GND
32 Vcc
28 Vcc
27 Vcc
1
2
3
4
24 N/C
23 N[1]
22 N[0]
21 M[8]
32-LEAD LQFP
5
6
7
8
20 M[7]
19 M[6]
18 M[5]
17 M[4]
10
12
13
14
15
M[3]
M[0]
M[1]
M[2]
OE
XTAL2
P_LOAD
N/C
16
11
9
SW01012
PIN DESCRIPTION
SYMBOL
XTAL1, XTAL2
S_LOAD (Int. pulldown)
S_DATA (Int. pulldown)
S_CLOCK (Int. pulldown)
P_LOAD (Int. pullup)
M[8:0] (Int. pullup)
N[1:0] (Int. pullup)
OE (Int. pullup)
F
OUT
, F
OUT
TEST
V
CC1
and V
CCO
PLL_V
CC
GND
FUNCTION
These pins form an oscillator when connected to an external series-resonant crystal.
This pin loads the configuration latches with the contents of the shift registers. The latches will be
transparent when this signal is HIGH, thus the data must be stable on the HIGH-to-LOW transition
of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the
rising edge.
This pin loads the configuration latches with the contents of the parallel inputs. The latches will be
transparent when this signal is LOW, thus the parallel data must be stable on the LOW-to-HIGH
transition of P_LOAD for proper operation.
These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH
transition of P_LOAD, M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled on the
LOW-to-HIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse
generation on the F
OUT
output.
These differential positive-referenced ECL signals (PECL) are the output of the synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
This is the positive supply for the internal logic and the output buffer of the chip, and is connected to
+3.3 V (V
CC
= PLL_V
CC
).
This is the positive supply for the PLL, and should be as noise-free as possible for low-jitter
operation. This supply is connected to +3.3 V (V
CC
= PLL_V
CC
).
These pins are the negative supply for the chip and are normally all connected to ground.
2002 Jun 03
4
Philips Semiconductors
Product data
25–400 MHz differential PECL clock generator
PCK12429
BLOCK DIAGRAM
+3.3 V
DIV 16
1 MHz
F
REF
PLL_V
CC
PHASE
DETECTOR
+3.3 V
VCO
XTAL1
16 MHz
OSC
XTAL2
9-BIT DIV M
COUNTER
DIV N
(1, 2, 4, 8)
V
CC0
F
OUT
F
OUT
200–400
MHz
OE
TEST
LATCH
LATCH
S_LOAD
P_LOAD
0
1
0
1
LATCH
N[1:0]
3-BIT
SR
0 0
0 1
1 0
1 1
Output Division
1
2
4
8
S_DATA
S_CLOCK
V
CC1
9-BIT
SR
2-BIT
SR
9
+3.3 V
M[8:0]
2
N[1:0]
SW00728
PROGRAMMING INTERFACE
Programming the device amounts to properly configuring the internal
dividers to produce the desired frequency at the outputs. The output
frequency can be represented by this formula:
F
OUT
= (F
XTAL
÷
16)
×
M
÷
N
(1)
Where F
XTAL
is the crystal frequency, M is the loop divider modulus,
and N is the output divider modulus. Note that it is possible to select
values of M such that the PLL is unable to achieve loop lock. To
avoid this, always make sure that M is selected to be 200
≤
M
≤
400
for a 16 MHz input reference.
Assuming that a 16 MHz reference frequency is used, the above
equation reduces to:
F
OUT
= M
÷
N
Substituting the four values for N (1, 2, 4, or 8) yields:
F
OUT
= M, F
OUT
= M
÷
2,
F
OUT
= M
÷
4 and F
OUT
= M
÷
8
for 200
≤
M
≤
400
The user can identify the proper M and N values for the desired
frequency from the above equations. The four output frequency
ranges established by N are 200–400 MHz, 100–200 MHz,
50–100 MHz, and 25–50 MHz respectively. From these ranges the
user will establish the value of N required, then the value of M can
be calculated based on the appropriate equation above. For
example, if an output frequency of 131 MHz was desired, the
following steps would be taken to identify the appropriate M and N
values. 131 MHz falls within the frequency range set by an N value
2002 Jun 03
5
of 2 so N [1:0] = 01. For N = 2 F
OUT
= M
÷
2 and M = 2
×
F
OUT
.
Therefore, M = 131
×
2 = 262, so M[8:0] = 100000110. Following this
same procedure a user can generate any whole frequency desired
between 25 and 400 MHz. Note that for N
≥
2 fractional values of
F
OUT
can be realized. The size of the programmable frequency
steps (and thus the indicator of the fractional output frequencies
achievable) will be equal to F
XTAL
÷
16
÷
N.
For input reference frequencies other than 16 MHz, the set of
appropriate equations can be deduced from equation 1. For
computer applications another useful frequency base would be
16.666 MHz. From this reference, one can generate a family of
output frequencies at multiples of the 33.333 MHz PCI clock. As an
example, to generate a 133.333 MHz clock from a 16.666 MHz
reference, the following M and N values would be used:
F
OUT
= 16.666
÷
16
×
M
÷
N = 1.041625
×
M
÷
N
Let N = 2, M = 256,
F
OUT
= 1.041625
×
256
÷
2 = 133.328 MHz
The value for M falls within the constraints set for PLL stability,
therefore N[1:0] = 01 and M[8:0] = 100000000. If the value for M fell
outside of the valid range a different N value would be selected to try
to move M in the appropriate direction.
The M and N counters can be loaded either through a parallel or
serial interface. The parallel interface is controlled via the P_LOAD
signal such that a LOW to HIGH transition will latch the information
present on the M[8:0] and N[1:0] inputs into the M and N counters.
When the P_LOAD signal is LOW the input latches will be
transparent and any changes on the M[8:0] and N[1:0] inputs will
京公网安备 11010802033920号
EEWORLD
