1. GENERAL DESCRIPTION .......................................................................................................................................... 1
1.1 APPLICATIONS FOR THE PCI 9080...................................................................................................................... 2
1.1.2 Embedded Systems ......................................................................................................................................... 2
1.2 MAJOR FEATURES ............................................................................................................................................... 3
1.3 COMPATIBILITY OF PCI 9080 WITH PCI 9060, 9060ES, AND 9060SD ................................................................ 4
1.4 COMPARISON OF PCI 9060, PCI 9060ES, PCI 9060SD, AND PCI 9080 .............................................................. 5
2. BUS OPERATION ....................................................................................................................................................... 6
2.1 PCI BUS CYCLES .................................................................................................................................................. 6
2.1.2.2 Direct Local to PCI Command Codes.......................................................................................................................... 6
2.2 LOCAL BUS CYCLES ............................................................................................................................................ 7
2.2.1 Local Bus Direct Master.................................................................................................................................... 7
2.2.2 Local Bus Direct Slave...................................................................................................................................... 7
2.2.2.1 Ready/Wait State Control ........................................................................................................................................... 7
2.2.2.4 Local Bus Read Accesses........................................................................................................................................... 8
2.2.2.5 Local Bus Write Accesses........................................................................................................................................... 8
2.2.2.6 Direct Slave Write Accesses—8- and 16-Bit Buses ..................................................................................................... 8
2.2.2.7 Local Bus Data Parity ................................................................................................................................................. 8
2.2.2.8 Local Bus Little/Big Endian ......................................................................................................................................... 8
2.2.2.8.1 32 Bit Local Bus—Big Endian Mode ..................................................................................................................... 8
2.2.2.8.2 16 Bit Local Bus—Big Endian Mode ..................................................................................................................... 8
2.2.2.8.3 8 Bit Local Bus—Big Endian Mode ....................................................................................................................... 9
3.1.1 PCI Bus Input RST# ....................................................................................................................................... 10
3.1.2 Local Bus Input LRESETi# ............................................................................................................................. 10
3.1.3 Local Bus Output LRESETo# ......................................................................................................................... 10
3.2.2 Local Initialization ........................................................................................................................................... 10
3.3.1 Short EEPROM Load ..................................................................................................................................... 11
3.3.2 Long EEPROM Load ...................................................................................................................................... 11
3.3.3 Extra Long EEPROM Load............................................................................................................................. 13
3.4.1 PCI Bus Access to Internal Registers ............................................................................................................. 13
3.4.2 Local Bus Access to Internal Registers ........................................................................................................... 14
3.5 DIRECT DATA TRANSFER MODES .................................................................................................................... 14
3.5.1 Direct Master Operation (Local Master to PCI Target)..................................................................................... 15
3.5.1.6 CFG (PCI Configuration Type 0 or Type 1 Cycles) .................................................................................................... 16
3.5.1.7 Direct Bus Master Lock ............................................................................................................................................. 16
3.5.1.9 Write and Invalidate.................................................................................................................................................. 16
3.5.2 Direct Slave Operation (PCI Master to Local Bus Access) .............................................................................. 18
3.5.2.1 PCI to Local Address Mapping .................................................................................................................................. 18
3.5.2.1.2 Local Bus Initialization Software ......................................................................................................................... 19
3.5.2.3 Direct Slave Lock...................................................................................................................................................... 22
3.5.3 Direct Slave Priority ........................................................................................................................................ 22
3.6.3 DMA Data Transfers....................................................................................................................................... 25
3.6.3.1 Local to PCI Bus DMA Transfer ................................................................................................................................ 25
3.6.3.2 PCI to Local Bus DMA Transfer ................................................................................................................................ 26
3.6.6.1 End of Transfer (EOT0# or EOT1#) Input.................................................................................................................. 27
3.6.6.2 Local Latency and Pause Timers .............................................................................................................................. 27
3.10.1.1 Local Interrupt Input................................................................................................................................................ 28
3.10.2 Local Interrupts (LINTo#) .............................................................................................................................. 29
3.10.2.1 Local to PCI Doorbell Interrupt ................................................................................................................................ 29
3.10.2.2 PCI to Local Doorbell Interrupt ................................................................................................................................ 29
3.10.2.3 Built In Self Test Interrupt (BIST)............................................................................................................................. 29
O Pointer Management .............................................................................................................................. 31
3.11.4 Inbound Free List FIFO................................................................................................................................. 32
3.11.5 Inbound Post List FIFO................................................................................................................................. 34
3.11.6 Outbound Post List FIFO .............................................................................................................................. 34
3.11.7 Outbound Free List FIFO.............................................................................................................................. 34
4.3.9 (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses
to Local, Runtime, and DMA Registers .................................................................................................................... 52
4.3.10 (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses
to Local, Runtime, and DMA Registers .................................................................................................................... 52
4.3.11 (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses
to Local Address Space 0........................................................................................................................................ 53
4.3.12 (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses
to Local Address Space 1........................................................................................................................................ 54
4.3.13 (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Register.......................................................................... 54
4.3.14 (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Register.......................................................................... 54
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